Browsing by Author "Cheng, Yi-Kan"

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Configurable Analog Routing Methodology via Technology and Design Constraint Unification
(2012)
Pan, Po-Cheng
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Chen, Hung-Ming
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Cheng, Yi-Kan
;
Liu, Jill
;
Hu, Wei-Yi
In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. In contrast to self-defined constraint format in prior arts, proposed approach manipulates the analog routing characteristic based on the unified constraints. In different circuit hierarchies defined by circuit designers or extracted by existing placement, the hierarchical structure is formed as specific analog layout constraint groups. This work efficiently facilitates analog routing strategy which honors the specific analog constraints. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.
Coupling- and ECP-Aware Metal Fill for Improving Layout Uniformity in Copper CMP
(2009)
Co, Yu-Lun
;
Chen, Hung-Ming
;
Cheng, Yi-Kan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
With feature sizes on chips shrinking at advanced process nodes, the difficulty in manufacturability and reliability of chips is extremely increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yields. The common solution to minimize topography variation is to perform metal fills in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/crosstalk noise problems. Furthermore, the impact of ECP (electroplating) should be included in the copper CMP model in order to have accurate metal fill results. In this paper, we adopt and implement an approach to considering especially the key layout parameters that affect the post-ECP topography. We further apply a greedy-based method to place the floating dummy metals in the positions with minimal additional coupling capacitances. The experimental results are encouraging. Our method not only considers the thickness range of post-ECP, it can also add much less additional coupling capacitances over a density-driven metal fill method.