Browsing by Author "Chern, HN"

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A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset
(1996-05-01)
Lai, CS
;
Lee, CL
;
Lei, TF
;
Chern, HN
;
電子工程學系及電子研究所
A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.
On designing of 4-valued memory with double-gate TFT
(1995)
Lee, CL
;
Chern, HN
;
Liao, MS
;
Wang, HM
;
電子工程學系及電子研究所