Browsing by Author "Chern, Mason"

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Layout-Based Dual-Cell-Aware Tests
(2019-01-01)
Wu, Tse-Wei
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Lee, Dong-Zhen
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Wu, Kai-Chiang
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Huang, Yu-Hao
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Chen, Ying-Yen
Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
(2019-01-01)
Nien, Yu-Teng
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Wu, Kai-Chiang
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Lee, Dong-Zhen
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Chen, Ying-Yen
;
Chen, Po-Lin
In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (ltf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify "more realistic" faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.