Browsing by Author "Chi, HF"

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A cost-effective memory-based real-valued FFT and hermitian symmetric IFFT processor for DMT-based wire-line transmission systems
(2005)
Chi, HF
;
Lai, ZH
;
電信工程研究所
;
Institute of Communications Engineering
This paper presents an efficient computation scheme for the memory-based FFT/IFFT processor used in DMT (discrete multi-tone) systems. Only half-size FFT/IFFT is required to transform real-valued data and Hermitain symmetric data. That is, the cost in processing elements and memory can be reduced by two. Finally, a variable-size radix-4 memory-based FFT/IFFT processor with block scaling scheme is designed for DMT systems.
A low-complexity B-spline based digital sample rate conversion circuit architecture
(2005)
Lin, CC
;
Chi, HF
;
電信工程研究所
;
Institute of Communications Engineering
This paper presents a low-complexity digital sample rate conversion (SRC) circuit architecture with arbitrary factor conversion ratio. The strategy in deciding SRC system parameters is given to guarantee that both the anti-imaging and the anti-aliasing requirements can be satisfied. The significant reduction in the complexity of the proposed structure allows simple VLSI implementation without affecting the performance. A parallel cascaded integrator comb (CIC) filter circuit without high intermediate sample rate and a multiplier-less linear interpolator are also developed to obtain a cost-effective and high-speed SRC circuit.