Browsing by Author "Chi, Hao-Yu"

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A Structure-Based Methodology for Analog Layout Generation
(2019-01-01)
Chen, Yu-Hsien
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Chi, Hao-Yu
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Song, Ling-Yen
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
In order to speed up analog design cycles, analog layout automation is a popular research in recent years. However, most previous works assume that the required design constraints are given by users manually. Designers still take a lot of time to fill-in the required design information. Template-based layout generation is another approach to consider the design constraints, but considerable development efforts are required for each new design and each new technology. In this paper, we propose a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users' input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users' intervention and still keeps the post-layout performance within specifications.
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines
(2019-01-01)
Chi, Hao-Yu
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Lin, Zi-Jun
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Hung, Chia-Hao
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
In order to improve design productivity, proper layout automation tools are desired for analog circuits. Layout migration is one possible approach to generate a new layout for given circuits with different device sizes or different technology, and still keep the original layout topology. However, routing behaviors are often not mentioned in previous works, which requires a complete rerouting that may not follow the original style. Pan [16] first proposed a Constrained Delaunay Triangulation (CDT) based model to keep the routing behavior during layout migration. However, because the device sizes and related distance may be different in the new layout, some reference lines in CDT models may be removed, resulting in some missing nets after migration. In this paper, a novel Cartesian Detection Line (CDL) based model is proposed to preserve the routing behavior in original layouts. Because alternative lines in the modified placement can be easily found to prevent from missing nets, the proposed CDL model greatly improves the routing completeness during layout migration. Several routing refinement techniques are also proposed to solve the routing issues due to block displacement. In our experiments, the routing completeness can be improved to almost 100% with the proposed CDL model, which greatly reduces the design efforts.
Analog Placement with Current Flow and Symmetry Constraints using PCP-SP
(2018-01-01)
Patyal, Abhishek
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Pan, Po-Cheng
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Asha, K. A.
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Chen, Hung-Ming
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Chi, Hao-Yu
Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This paper proposes the first work that reformulates this problem considering all of them together in the form of Parallel Current Path (PCP) constraints. Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. Experimental results show that this formulation and algorithm can satisfy all the constraints in a more tightly packed configuration, resulting in lesser routing length, reduced parasitics and thus better post-layout performance.
Performance-Preserved Analog Routing Methodology via Wire Load Reduction
(2018-01-01)
Chi, Hao-Yu
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Tseng, Hwa-Yi
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
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電子工程學系及電子研究所
Analog layout automation is a popular research direction in recent years to raise the design productivity. However, the research on this topic is still not well accepted by analog designers because notable performance loss often exists in tool-generated layout. Most previous works focus on layout placement problem and route the nets implicitly by typical digital routing methodology. This routing approach can solve the net crossing issue easily, but requires a lot of extra vias to connect the horizontal and vertical lines, which significantly increases the wire loads and reduces the circuit performance. In the proposed analog routing flow, we try to route each net with minimum layer changing and consider the wire length simultaneously. In other words, wire load is used as the optimization goal instead of using wire length only to keep the circuit performance after laying out the design. As demonstrated on several cases, this approach significantly reduces the wire load and keeps the similar circuit performance as in manual works.