Browsing by Author "Chiang, Bo-Yi"

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Timing-Constrained Yield-Driven Redundant Via Insertion
(2008)
Yan, Jin-Tai
;
Chen, Zhi-Wei
;
Chiang, Bo-Yi
;
Lee, Yu-Min
;
電信工程研究所
In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.