Browsing by Author "Chiang, CT"

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A Bayesian procedure for process capability assessment
(1999-09-01)
Shiau, JJH
;
Chiang, CT
;
Hung, HN
;
統計學研究所
;
Institute of Statistics
The usual practice of judging process capability by evaluating point estimates of some process capability indices has a flaw that there is no assessment on the error distributions of these estimates. However, the distributions of these estimates are usually so complicated that it is very difficult to obtain good interval estimates. In this paper we adopt a Bayesian approach to obtain an interval estimation, particularly for the index C(pm). The posterior probability p that the process under investigation is capable is derived; then the credible interval, a Bayesian analogue of the classical confidence interval, can be obtained. We claim that the process is capable if all the points in the credible interval are greater than the pre-specified capability level omega, say 1.33. To make this Bayesian procedure very easy for practitioners to implement on manufacturing floors, we tabulate the minimum values of (C) over cap(pm)/omega for which the posterior probability p reaches the desirable level, say 95%. For the special cases where the process mean equals the target value for C(pm) and equals the midpoint of the two specification limits for C(pk). the procedure is even simpler; only chi-square tables are needed. Copyright (C) 1999 John Wiley & Sons, Ltd.
A CMOS focal-plane retinal sensor designed for shear motion detection
(2004-01-01)
Wu, CY
;
Hsieh, WC
;
Chiang, CT
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a CMOS focal-plane shear sensor is designed and implemented. The adopted motion computation method is based on correlation-based algorithms with modification to detect the local motion vectors and the adopted retinal processing circuit is to sense and preprocess the incident image. The proposed shear sensor has a shear-motion-like structure to be selective to the direction and velocity of the images. There are totally 76 pixels, which form four shearmotion detection pairs. The area of a single pixel is 52.96 x 55.07 mm 2 with a fill factor of 16%. The chip area is 1151 x 1116 mm 2.
A CMOS focal-plane retinal sensor designed for shear motion detection
(2004-01-01)
Wu, CY
;
Hsieh, WC
;
Chiang, CT
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a CMOS focal-plane shear sensor is designed and implemented. The adopted motion computation method is based on correlation-based algorithms with modification to detect the local motion vectors and the adopted retinal processing circuit is to sense and preprocess the incident image. The proposed shear sensor has a shear-motion-like structure to be selective to the direction and velocity of the images. There are totally 76 pixels, which form four shearmotion detection pairs. The area of a single pixel is 52.96 x 55.07 mm 2 with a fill factor of 16%. The chip area is 1151 x 1116 mm 2.
A low-photocuffent CMOS retinal focal-plane sensor with a pseudo-BJT smoothing network and an adaptive current Schmitt trigger for scanner applications
(2004-08-01)
Wu, CY
;
Chiang, CT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt trigger is proposed. The proposed structure is very simple and compact. This new circuit can easily be implemented in CMOS technology with a small chip area. Another innovation of this circuit is that the proposed circuit could be operated for low-induced current levels (pA), and the current hysteresis of the proposed current Schmitt trigger could be adjusted adaptively according to the value of induced photocurrents. In this work, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes a 32 x 32 pixel array with a pixel size of 70 x 70 mum(2). The fill factor is 75% and the total chip area is 3000 x 3030 mum(2). It is with fully functional 32 x 32 implementations consuming less than 8.8 muW per pixel at 3.3 V. Measurement results show that the proposed new retinal focal-plane sensor has successfully been used in character recognition of scanner systems, such as pen scanners, etc.
A low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt trigger for scanner applications
(2003)
Wu, CY
;
Chiang, CT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt trigger is proposed. The proposed structure is very simple and compact. This new circuit can be easily implemented in CMOS technology with a small chip area. Besides, another innovation of this circuit is that the proposed circuit could be operated for low-induced current level (pA), and the current hysteresis of proposed current Schmitt trigger could be adjusted adaptively according to the value of induced photocurrent. In this paper, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes 32 x 32 pixel array with a pixel size of 70 x 70 mum(2). The fill factor is 75% and the total chip area is 3000 x 3030 mum(2). It is with fully functional 32 x 32 implementations consuming less than 8.8 muW per pixel at 3.3 V. Measurement results present the proposed retinal focal-plane sensor could be successfully used in character recognition, such as pen-scanner or etc.
A note on Bayesian estimation of process capability indices
(1999-11-15)
Shiau, JJH
;
Hung, HN
;
Chiang, CT
;
統計學研究所
;
Institute of Statistics
Process capability indices are useful for assessing the capability of manufacturing processes. Most traditional methods are obtained from the frequentist point of view. We view the problem fi om the Bayes and empirical Bayes approaches by using non-informative and conjugate priors, respectively. (C) 1999 Elsevier Science B.V. All rights reserved.
Design and implementation for the prototype of a microstimulator
(2003-05-01)
Chiang, CT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, the first domestic implementation of an implantable microstimulator utilizing HDL and ASIC methodologies is presented. We implement the digital part of the microstimulator by writing the hardware description language for the digital circuits, synthesizing them and downloading them into a field programmable gate array. The analog part is designed by using full-custom IC design flow, implemented by CMOS 0.35 mum technology, and fabricated by TSMC. It generates a maximum current of 2.77 mA through 1 kOmega load while the stimulation frequency is 20Hz and the stimulation current pulse width is 300 mus, and the maximum power consumption is evaluated at 14 mW based on a 5 V voltage supply.
Implantable neuromorphic vision chips
(2004-03-18)
Chiang, CT
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The implantable neuromorphic vision chips are analysed and implemented. These proposed analogue integrated circuits are to implement four cell functions of the retina for implant. These retinal cells are photoreceptor cells, horizontal cells, bipolar cells, and ganglion cells. All simulation results are successfully verified and consistent with researches on biological retinas.