Browsing by Author "Chiang, Chien-Hsueh"

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A Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industry
(2016-10)
Chiang, Chien-Hsueh
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this study, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display. The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a five-mask amorphous silicon process for thin-film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.
Circuit-Simulation-Based Multi-Objective Evolutionary Algorithm for Design Optimization of a-Si:H TFTs Gate Driver Circuits Under Multilevel Clock Driving
(2015-08-01)
Hung, Sheng-Chin
;
Chiang, Chien-Hsueh
;
Li, Yiming
;
傳播研究所
;
電機資訊學士班
This work optimizes dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator running on the platform of unified optimization framework (UOF). The ASG driver circuit consisting of 17 a-Si:H TFTs is optimized for the given specifications of the fall time <3 mu s and the ripple voltage < - 9 V while simultaneously minimizing the total layout area. More than 50% reductions on the fall time of the ASG driver circuit have been achieved by using the optimization methodology together with a novel three-level clock driving technique. The measured results of the fabricated sample using the optimized parameters confirm the practicability of reported MOEA methodology.
Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si:H TFTs Gate Driver Circuit Design Optimization
(2015-01-01)
Hung, Sheng-Chin
;
Chen, Chieh-Yang
;
Chiang, Chien-Hsueh
;
Li, Yiming
;
分子醫學與生物工程研究所
In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 mu s and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.
Design, Fabrication and Characterization of Low-Noise and High-Reliability Amorphous Silicon Gate Driver Circuit for Advanced FPD Applications
(2015-08-01)
Chiang, Chien-Hsueh
;
Li, Yiming
;
傳播研究所
;
電機資訊學士班
;
Institute of Communication Studies
We report a novel design of amorphous silicon gate (ASG) driver circuit with not only low output noises but also improved reliability. The ASG circuits are made of thin-film transistors (TFTs) and integrated in the substrate glass. Unlike the most traditional ASG circuits, the proposed pull-down signals are complementary with lower frequency to discharge the critical nodes in the proposed circuit. The new pull-down signals are created to discharge each two adjacent stage circuits. By inputting two controlled pulse signals, the prospective pull-down signals can be created eventually in the circuit. To simulate the real driving conditions, a string of a resistance (1.24 k Omega) and a capacitance (85.5 pF) are connected to each output as loading. By probing the output pads of the real circuit sample, the output characteristics can practicably be measured. In particular, the output ripples can be suppressed to 0.28 V. Moreover, the measured threshold voltage (V-th)shift with two stressing signals at different frequencies reveals the significant difference. The measured V-th shift after 12 h of the clock stressing with lower frequency (167 Hz) is about 12% slower speed than that of the stressing clock with higher frequency (16.7 kHz) under the high temperature (60 degrees C).
Low Power and High Driving Capability of Amorphous Silicon Gate Driver Circuit
(2016-01)
Chiang, Chien-Hsueh
;
Li, Yiming
;
交大名義發表
;
傳播研究所
;
電機學院
In this paper, we propose a novel amorphous silicon gate driver (ASG) circuit with useful driving methods in saving power consumption and improving driving capability as well. Unlike other driving methods that are used to improve the driving capability also increases the power consumption strikingly. In this paper, an ASG circuit with novel driving method is proposed and realized in standard 5-mask hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) process. The circuit consisting of 13 a-Si: H TFTs is used in portable flat-panel displays (FPDs) for the high driving capability and low power characteristic. By comparing other driving methods, the results of the definitive measurement show that the minimum driving high voltage is improved with 2 volts increment and the power consumption increases 9.7% slightly. Moreover, the other dynamic characteristics of the ASG, such as the rise time and fall time of the outputs, can be improved at the same time. To validate the results, the designate circuit is fabricated with 5-mu m a-Si:H TFT process and the experimental results confirm the practicability of achieved design. Three different driving methods are adopted in the same ASG circuit to respond three individual output characteristics.