Browsing by Author "Chiang, Chih-Hsuan"

Now showing 1 - 3 of 3

A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems
(2018-01-01)
Chiang, Chih-Hsuan
;
Huang, Shuo-An
;
Chen, Chiao-En
;
Yang, Chia-Hsiang
;
電子工程學系及電子研究所
The generalized geometric mean decomposition (GGMD) is a recently proposed matrix decomposition which can be viewed as a computationally efficient counterpart of the conventional geometric mean decomposition (GMD). As the GMD is the core algorithm in many high performance precoders and equalizers such as the Tomlinson-Harashima precoder and decision feedback equalizer, GGMD facilitates a more computationally efficient implementation while exhibiting identical performance. This work presents the first GGMD processor in the open literature, supporting various matrix sizes by leveraging the reconfigurable processing element (PE) using coordinate rotation digital computers (CORDICs). The implemented GGMD processor supports matrix sizes of 2(n) which ranges from 2 x 2 to 16 x 16, and the throughput performance is maximized through a PE array architecture. The chip integrates 326.9K gates in an area of 1.65 mm(2) in a 90-nm CMOS technology with the maximum throughput achieving 450K matrices/sec for a 16 x 16 matrix at 125 MHz. It dissipates 20.7-28.5 mW at 125 MHz from a 1V supply. Compared to previous GMD designs, this work supports a larger MIMO system with lower hardware complexity and power consumption.
Classifier Grouping to Enhance Data Locality for A Multi-Threaded Object Detection Algorithm
(2011)
Lai, Bo-Cheng Charles
;
Chiang, Chih-Hsuan
;
Li, Guan-Ru
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Object detection has become an enabling function for modern smart embedded devices to perform intelligent applications and interact with the environment appropriately and promptly. However, the limited computation resource of embedded devices has become a barrier to execute the computation intensive object detection algorithm. Leveraging the multi-threading scheme on embedded multi-core systems provides an opportunity to boost the performance. However, the memory bottleneck limits the performance scalability. Improving data locality of applications and maximizing the data reuse for on-chip caches have therefore become critical design concerns. This paper comprehensively analyzes the memory behavior and data locality of a multi-threaded object detection algorithm. A novel Classifier-Grouping scheme is proposed to significantly enhance the data reuse for on-chip caches of embedded multi-core systems. By executing a multi-threaded object detection algorithm on a cycle-accurate multi-core simulator, the proposed approach can achieve up to 62% better performance when compared with the original parallel program.
Multi-Level Parallelism Analysis of Face Detection on a Shared Memory Multi-Core System
(2011)
Chiang, Chih-Hsuan
;
Kao, Chih-Heng
;
Li, Guan-Ru
;
Lai, Bo-Cheng Charles
;
電子工程學系及電子研究所
Face detection is one of the fundamental technologies for the future smart objects. However, its computation intensive property thwarts the practice of a real-time application on an embedded device. Parallel processing and many-core architecture have become a mainstream to achieve high performance in the future computing systems. The parallelism of an application needs to be exposed before being exploited by the parallel architecture. This paper performs a comprehensive analysis of the parallelism of a face detection algorithm at different algorithmic levels. This paper has demonstrated that each parallelism level has its own potential to enhance performance, but also imposes different limiting factors to the overall performance. Based on the analysis results and design experience, this paper proposes a multi-staged mixed-level parallelization scheme to retain the performance scalability and avoid the limiting factors. With this scheme, we are able to achieve up to 37.5x performance enhancement on a 64-core system.