Browsing by Author "Chiang, HC"

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A digital camcorder image stabilizer based on gray coded bit-plane block matching
(2000)
Yeh, YM
;
Wang, SJ
;
Chiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we proposed an efficient algorithm to do image stabilization for digital camcorder. This approach is based on gray-coded bit-plane block matching to eliminate the unpleasing effect caused by involuntary movement of camera holders. To improve moving object detection and stabilization performance, a frame is divided into several blocks to do localized motion estimation. Based on our architecture, the temporal correlation is used at the motion unit to efficiently detect moving objects and panning conditions. To compensate for camera rotation, an energy minimization is also applied to calculate the coefficients of affine transform without many complicated computations. Having considered both programming flexibility and hardware efficiency, the motion decision and motion compensation units are coded in a microprocessor that interconnects with the stabilization hardware. The proposed stabilizer is now implemented on FPGA 10K 100.
Digital camcorder image stabilizer based on gray-coded bit-plane block matching
(2001-10-01)
Yeh, YM
;
Chiang, HC
;
Wang, SJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We propose an efficient algorithm to eliminate the nonpleasing effect caused by involuntary hand movement of camera holders. In our approach, 1-bit gray-coded bit-plane block matching, instead of 8-bit gray-level block matching, is used to greatly simplify the computation of motion estimation. This computation saving makes possible a finer division of image frame and thus facilitates the employment of a much more robust procedure for motion decision. To deal with various interfering factors in motion estimation, the temporal information of each local motion vector is also used to efficiently distinguish random-like movement from temporally correlated movement. To compensate for camera rotation, an affine model is used in the motion compensation unit without adding too much computation load. Having considered both programming flexibility and hardware efficiency, the motion decision unit and the motion compensation unit are coded in a microprocessor that interconnects with the stabilization hardware, which consists of the motion estimation unit and the digital zooming unit. A slightly simplified version of the proposed stabilizer is implemented on a field programmable gate array (FPGA) board. (C) 2001 Society of Photo-Optical Instrumentation Engineers.