Browsing by Author "Chiang, Hsiao-Cheng"

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A Dual-Gate InGaZnO4-Based Thin-Film Transistor for High-Sensitivity UV Detection
(2019-08-01)
Chen, Po-Hsun
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Tsao, Yu-Ching
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Chien, Yu-Chieh
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Chiang, Hsiao-Cheng
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Chen, Hua-Mao
UV-sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product commercialization is determining the optimal materials that allow for integration of excellent UV-sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV-light-sensing properties of an amorphous InGaZnO4 (IGZO) thin-film transistor with a dual-gate structure and relatively small device size (width/length = 50 mu m/10 mu m) that achieves high sensitivity through a threshold-voltage-(V-th)-adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 10(6). Furthermore, the UV sensitivity of the dual-gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual-gate a-IGZO transistor to be used for high-performance UV sensing while being effectively integrated in display applications.
Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors
(2017-01-09)
Tsao, Yu-Ching
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chiang, Hsiao-Cheng
This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software. Published by AIP Publishing.
Effect of SiO2 Buffer Layer Thickness on Performance and Reliability of Flexible Polycrystalline Silicon TFTs Fabricated on Polyimide
(2016-12-01)
Chen, Bo-Wei
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Chang, Ting-Chang
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Hung, Yu-Ju
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Huang, Shin-Ping
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Chen, Hua-Mao
This letter investigates flexible polycrystalline silicon thin film transistor performance variation due to different buffer layer thicknesses. In flexible electronics, thermal expansion stress during device fabrication is inevitable. A thicker SiO2 buffer demonstrates better endurance to thermal expansion stress from the polyimide substrate during device annealing. However, if the SiO2 buffer thickness is above a critical point, its weak heat dissipation capability causes the optimal ELA crystallization condition to shift. A thermal expansion stress simulation and TEM photos were utilized to verify performance variation. Furthermore, a similar trend was observed in electrical characteristics after negative bias temperature instability.
Gate Insulator Morphology-Dependent Reliability in Organic Thin-Film Transistors
(2016-02)
Chen, Hua-Mao
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Chang, Ting-Chang
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Tai, Ya-Hsiang
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Chiang, Hsiao-Cheng
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Liu, Kuan-Hsien
In this letter, we investigated the gate insulator morphology affecting on the electric characteristic variation for organic thin-film transistors (OTFTs). From the transfer characteristics, there is a result with leakage current when the gate voltage is lower than the threshold voltage, which is due to the gate insulator thickness variation. Furthermore, regardless of whether the OTFT is operated under positive or negative bias stress, the more severe degradation happened in the hump region of transfer characteristics. Because a thinner gate insulator causes a high electric field, more charges are trapped in a gate dielectric stack.
Identical Off-state Current Raise Induced by Photo-induced Schottky Barrier Lowering in a-InGaZnO4 Thin Film Transistors
(2016)
Chen, Hua-Mao
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Chang, Ting-Chang
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Liao, Po-Yung
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Chiang, Hsiao-Cheng
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Chen, Ching-En
This work studies the mechanism of identical photoinduced leakage current in a-InGaZnO4 thin film transistors during reverse gate voltage sweep. There is the identical off-state current with the reverse sweep under UV light irradiation, and the photocurrent for UV light exposure region near the source electrode is more significant than that near the drain electrode, which is different from photocurrent mechanism of low temperature polysilicon TFTs. This is because the photo-generated electrons increase the carrier concentration in a-InGaZnO4 bulk, causing the reduced depletion width of the active layer. Therefore, the back channel of active layer is out of gate control.
Improvements in the reliability of a-InGaZnO thin-film transistors with triple stacked gate insulator in flexible electronics applications
(2015-11-30)
Chen, Hua-Mao
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Chang, Ting-Chang
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Tai, Ya-Hsiang
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Chen, Kuan-Fu
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Chiang, Hsiao-Cheng
This study examined the impact of the low-temperature stacking gate insulator on the gate bias instability of a-InGaZnO thin film transistors in flexible electronics applications. Although the quality of SiNx at low process/deposition temperature is better than that of SiOx at similarly low process/deposition temperature, there is still a very large positive threshold voltage (V-th) shift of 9.4 V for devices with a single low-temperature SiNx gate insulator under positive gate bias stress. However, a suitable oxide-nitride-oxide-stacked gate insulator exhibits a Vth shift of only 0.23 V. This improvement results from the larger band offset and suitable gate insulator thickness that can effectively suppress carrier trapping behavior. (C) 2015 Elsevier B.V. All rights reserved.
Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors
(2017-09-25)
Chiang, Hsiao-Cheng
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Chang, Ting-Chang
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Liao, Po-Yung
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Chen, Bo-Wei
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Tsao, Yu-Ching
This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO4 thin film transistors with copper electrodes. After 2000 s of NBTS, an abnormal subthreshold swing and on-current (I-on) degradation is observed. The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer. Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis. Published by AIP Publishing.
Role of H2O Molecules in Passivation Layer of a-InGaZnO Thin Film Transistors
(2017-04-01)
Chien, Yu-Chieh
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Chang, Ting-Chang
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Chiang, Hsiao-Cheng
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Chen, Hua-Mao
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Tsao, Yu-Ching
This letter analyzes performance and reliability of inverted staggered type amorphous indium-gallium-zinc oxide devices in a moist environment with H2O molecules in the passivation layer. There is a negative threshold voltage shift (Delta Vth) in the saturation region (V-D = 10 V), which increases with decreasing channel length. We propose that this is explained by the drain-induced barrier lowering that is due to the H2O molecules. Moreover, a hydrogen bonding model under bias stress is also proposed, in contrast to the conventional H2O doping model. Recovery behavior after bias stress and ac operation were utilized to distinguish the difference between these models.
Surface Engineering of Polycrystalline Silicon for Long-Term Mechanical Stress Endurance Enhancement in Flexible Low Temperature Poly-Si Thin-Film Transistors
(2017-04-05)
Chen, Bo-Wei
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Chang, Ting-Chang
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Chang, Kuan-Chang
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Hung, Yu-Ju
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Huang, Shin-Pin
The surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing longterm mechanical stress and the influence of stress on electrical characteristics. Our simulated results show that the nonuniform stress in the gate insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a nonuniform degradation phenomenon, which affects both the performance and the reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the subchannel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with the lowest protrusions demonstrates the smallest degradation after undergoing long-term bending.