Browsing by Author "Chiang, Kuang-Hao"
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Item type:Item, A Comprehensive Study of 3-stage High Resistance State Retention Behavior for TMO ReRAMs from Single Cells to a Large Array(2017-01-01) ;Lin, Yu-Hsuan ;Ho, Yung-Han ;Lee, Ming-Hsiu ;Wang, Chao-HungLin, Yu-YuFor the first time the retention of high resistance state (HRS) in resistive random access memory (ReRAM) is found to compose of three stages - extending tail-bits, distribution shift, and then distribution broadening. This work provides a comprehensive study on the HRS's retention behavior in WOx-based ReRAMs from single device characteristics to group distribution. Different from conventional activation energy (Ea) analysis, the mean and variance of the array distribution are presented to overcome the non-uniform Ea issue. Since the extracted Ea fits well with Vo(2+) (oxygen vacancy) migration characteristics, the three retention stages are suggested to be the competing results from the migration, recombination, and generation of the Vo(2+) and O2- in the gap region. A three-dimensional retention model with kinetic Monte Carlo simulator and trap-assisted tunneling conduction is proposed to discuss the dominating mechanism in different time and temperature scales. The mechanism for random telegraph noise is also included to illustrate the fluctuating nature of the HRS cells.Item type:Item, A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM(2016-11) ;Lin, Yu-Hsuan ;Lee, Ming-Hsiu ;Wu, Jau-Yi ;Lin, Yu-YuLee, Feng-MingResistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WOx ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WOx ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (-40 degrees C-125 degrees C), suitable for high-reliability applications.Item type:Item, Excellent High Temperature Retention of TiOXNV ReRAM by Interfacial Layer Engineering(2018-01-01) ;Lin, Yu-Hsuan ;Lee, Dai-Ying ;Wang, Chao-Hung ;Lee, Ming-HsiuHo, Yung-HanSince the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on thc interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiO Ny ReRAM to block the diffusion of oxygen ions through the Ti/TiO,N interface. The mechanism and factors that influenced thc IIRS and LRS retention arc also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiO,N, ReRAMs can switch for more than 103 cycles from array testing results.Item type:Item, Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm(2016) ;Lin, Yu-Hsuan ;Wu, Jau-Yi ;Lee, Ming-Hsiu ;Wang, Tien-YenLin, Yu-YuTMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.Item type:Item, Threshold Vacuum Switch (TVS) on 3D-Stackable and 4F(2) Cross-Point Bipolar and Unipolar Resistive Random Access Memory(2012-01-01) ;Ho, ChiaHua ;Huang, Hsin-Hau ;Lee, Ming-Taou ;Hsu, Cho-LunLai, Tung-YenA 3D stackable and bidirectional Threshold Vacuum Switching (TVS) selector using the same WO x material as the RRAM element is reported. It provides the highest reported current density of >10(8) A/cm(2) and the highest selectivity of >10(5). Stress test at high current density indicates >10(8) cycle capability for Reset/Set operation. A mechanism based on recombination of oxygen-ions and vacancies is proposed for the observed volatile switching of TVS. Utilizing the threshold characteristics of the TVS selector, a two-step reading waveform offers potential for 3D-stackable and 4F(2) cross-point RRAM applications.