Browsing by Author "Chiang, Kuen-Cheng"

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Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips
(2018-04-01)
Lu, Guan-Ruei
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Kuo, Chun-Hao
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Chiang, Kuen-Cheng
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Banerjee, Ansuman
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Bhattacharya, Bhargab B.
The active matrix (AM)-based architecture offers many advantages over conventional digital electrowetting-on-dielectric (EWOD) microfluidic biochips, such as the capability of handling variable-size droplets, more flexible droplet movement, and precise control over droplet navigation. However, a major challenge in choosing the routing paths is to decide when the droplets are to be reshaped depending on the congestion of the intended path, or split- and route sub droplets,and merging them at their respective destinations. As the number of microelectrodes in AM-EWOD chips is large, the path selection problem becomes further complicated. In this article, we propose a negotiation-guided flow based on routing of subdroplets that obviates the explicit need for deciding when the droplets are to be manipulated, yet fully utilizing the power of droplet reshaping, splitting, and merging them to facilitate their journey. The proposed algorithm reduces routing cost and provides more freedom in deadlock avoidance in the presence of multiple routing tasks by assigning certain congestion penalty for sibling subdroplets and fluidic penalty for heterogeneous droplets. Compared to existing techniques, it reduces latest arrival time by an average of 29% for several benchmark and random test suites. Furthermore, our method is observed to provide 100% routability of nets for all test cases, whereas existing and baseline routers fail to produce feasible solutions in many instances. We also propose a reliable mode droplet routing strategy where the number of unreliable splitting operations can be reduced by paying a small penalty on latest arrival time.
Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems
(2012-02-01)
Chiang, Kuen-Cheng
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Wu, Ming Feng
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
In this paper, we propose an architecture for H.264/AVC fast intra-prediction-mode decision making in high resolution real-time applications. Intra-prediction-mode decision making requires many computations of H.264/AVC video coding, and also extra time for mode generation for intra prediction mode decisions. Hence, there exists a bottleneck in the execution of high resolution real-time applications. To improve the operation of intra prediction mode decision, we use an algorithm which, based on the edge information of an object, will reduce estimations of mode predictions by 66%; with negligible loss of video quality and a small increase in bit-rate of video stream. We propose a low cost architecture, with gate counts reduced by 50% compared with former design. The total gate count is 86,671 and the maximum operating frequency is 250 MHz using TSMC 0.18 mu m cell-based technology. The experimental results show our design is a strong competitor with most modern high resolution, real-time video processing. (C) 2011 Elsevier Inc. All rights reserved.
Run-time reconfiguration scheduling of 3D-rendering on a reconfigurable system
(2005)
Chiang, Kuen-Cheng
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Lee, Meng-Tho
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Shann, Jean Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
With the dramatically increasing demands for multimedia processing capabilities in portable electronic devices, the architectural supports for various multimedia computations in one platform are crucial to the success of a product. Although application-specific accelerators have performance advantages, their inflexibilities seriously impede the applicability and shorten product lifetime. On the other hand, a general-purpose processor has benefits to wide applicability but can not meet the real-time criteria in many cases. Therefore, we develop a platform consisting of a general-purpose CPU, an array of processing elements, and a shared memory to transfer data between them. In addition, we propose two scheduling methods, First-Come-First-Serve and Priority, to process the 3D models with a better performance. Experimental results indicate that the priority scheduling significantly improves the 3D-rendering in both computation speed and silicon area, compared with FCFS scheduling. Given the same speed requirements on both FCFS and priority scheduling methods, the priority scheduling requires only 75% of the silicon area. On the other hand, it yields 30% to 80% speedup with the same area. Moreover, with priority scheduling, its performance advantage can be further increased by skills such as partial reconfiguration and multi-context configuration, to reduce its reconfiguration overhead.