Browsing by Author "Chiang, T"

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A buffer-feedback rate control method for video streaming over mobile communication systems
(2005)
Tseng, LC
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Chuang, HC
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Huang, CY
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Chiang, T
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電子工程學系及電子研究所
In a wireless video streaming service system, the receiver reports its required rate in the reverse link for each transmission. A data buffer is often installed in the receiver to stabilize the multimedia play-out rate. This buffer may underflow if there is a shortage of content. Simply increasing the transmission rates may cause resource problems. A more delicate way is trying to control the transmission rate when necessary. In this paper, a transmission rate control method utilizing the receiver buffer fullness level and the frame error rate (FER) information is proposed. Simulation results demonstrate the proposed control provides better play-out quality with reasonable system resources consumption.
A fast audio bit allocation technique based on a linear R-D model
(2002-08-01)
Lee, CY
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Fang, YC
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Chuang, HC
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Wang, CN
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Chiang, T
The MPEG-1 Layer III audio coding is most widespread digital audio format on the Internet. Its encoder is more complicated than the other layers., in the MPEG-I audio specification, where the bit allocation constitutes significant part of the total computational load. This paper describes a fast bit allocation technique using a novel linear model to compute the bitrate and the global gain of the inner loop (rate control loop) for the classic MP3 bit allocation problem. Estimated quantization noise is approximated with a binomial expansion for the adjustment of the scalefactors. This procedure reduces the outer loop iterations (distortion control loop) to one loop. Our bit allocation technique is about five times faster compared to the well-known LAME MP3 encoder. Based on the objective quality measure, total number of distorted bands, and average total noise-to-masking ratio (NMR), our experimental results show that there is significant improvement in speedup of the encoding process without noticeable audio quality degradation.
A fast H.264-based picture-in-picture (PIP) transcoder
(2004)
Li, CH
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Lin, H
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Wang, CN
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Chiang, T
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電子工程學系及電子研究所
The paper presents a novel and fast transcoding scheme with PIP (Picture-in-Picture) functionality based on H.264/AVC standard. We seamlessly achieve significant speedup and maintain identical video quality for the composite video content using two H.264 bitstreams. The proposed Partial Re-Encoding transcoder (PRET) method based on the intra-prediction refinement, inter-prediction refinement and rate-distortion optimization has sped up by 8 times for with rate-distortion (R-D) based optimization. In addition, the performance of the PRET is better than that of R-D re-encoding algorithm.
A novel adaptive video playout control for video streaming over mobile cellular environment
(2005)
Chuang, HC
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Huang, C
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Chiang, T
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Video streaming is becoming one of the potential killer applications in a mobile service network. MPEG-4 Fine-Granularity Scalabitity is proposed to significantly increase the flexibility for video transmission. However, the bottleneck of bandwidth often occurs in the last-mile transmission from the base station to the mobile device, which incurs quality degradation. Adaptive Media Playout (AMP) is a receiver-based technique that could eliminate the buffer outage and hence improve the associated visual quality. This paper addresses the issue of AMP control utilized in a mobile cellular environment. Specifically, we propose a novel AMP control that could further improve the visual quality compared to other conventional AMP controls. Experimental results demonstrate the proposed control provides better visual quality with a low complexity.
A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC
(2005-02-01)
Chang, SC
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Peng, WH
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Wang, SH
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Chiang, T
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電子工程學系及電子研究所
In this paper, we proposed a platform based bus-interleaved architecture for the de-blocking filter in H.264. Specifically, to efficiently use the bus bandwidth, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfer. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transmission and filtering in parallel. As compared to the state-of-the-art designs, our scheme offers 1.6x to 7x performance improvement. While clocking at 100MHz, our design can support 2560x1280@30Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can be easily applied in system-on-chip design.
A software-hardware co-implementation of MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining
(2005-08-01)
Wang, SH
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Peng, WH
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He, YW
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Lin, GY
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Lin, CY
We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.
Platform based design of all binary motion estimation (ABME) with bus interleaved architecture
(2005)
Wang, SH
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Tao, WL
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Wang, CN
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Peng, WH
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Chiang, T
This paper presents an efficient hardware-software implementation with a marcoblock based pipelining and a bus interlaced architecture for all binary motion estimation (ABME), which has been proven to be simple and low cost for hardware design. The bus interleaved preprocessing module of the ABME architecture can generate downsampling and binarized data in the same flow without additional dedicated hardware. With the 3-layer binary bitplane of ABME, we use a two-dimensional (2-D) mapping unit and a binary adder tree instead of a systolic array to compute the block matching metric, which is sum of difference (SoD), in one cycle. In addition, a new bus bandwidth reduction scheme is proposed by reusing the binarized image, which can achieve up to 67% bus bandwidth saving. The experiment shows that for each macroblock, our design can finish ABME within 283 cycles with 65k gate counts synthesized by UMC 0.18 um cell library.
Scalable rate control for MPEG-4 video
(2000-09-01)
Lee, HJ
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Chiang, T
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Zhang, YQ
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交大名義發表
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National Chiao Tung University
This paper presents a scalable rate control (SRC) scheme based on a more accurate second-order rate-distortion model. A sliding-window method for data selection is used to mitigate the impact of a scene change. The data points for updating a model are adaptively selected such that the statistical behavior is improved. For video object (VO) shape coding, we use an adaptive threshold method to remove shape-coding artifacts for MPEC-4 applications. A dynamic bit allocation among VOs is implemented according to the coding complexities for each VO, SRC achieves more accurate bit allocation with low latency and limited buffer size. In a single framework, SRC offers multiple layers of controls for objects, frames, and macroblocks (MBs), At MB level, SRC provides finer bit rate and buffer control. At multiple VO level, SRC offers superior VO presentation for multimedia applications. The proposed SRC scheme has been adopted as part of the International Standard of the emerging ISO MPEG-I standard [1], [2].
Special Issue: Multimedia Content Description and Video Compression Technology. I
(2003)
Smith, JR
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Wiegand, T
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Chiang, T
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交大名義發表
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National Chiao Tung University