Browsing by Author "Chiang, Tihao"

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A context adaptive bit-plane coder with maximum-likelihood-based stochastic bit-reshuffling technique for scalable video coding
(2006-08-01)
Peng, Wen-Hsiao
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Chiang, Tihao
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Hang, Hsueh-Ming
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Lee, Chen-Yi
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電子工程學系及電子研究所
In this paper, we propose a context adaptive bit-plane coding (CABIC) with a stochastic bit reshuffling (SBR) scheme to deliver higher coding efficiency and better subjective quality for fine granular scalable (FGS) video coding. Traditional bit-plane coding in FGS algorithm suffers from poor coding efficiency and subjective quality. To improve coding efficiency, our CABIC constructs context models based on both the energy distribution in a block and the spatial correlations in the adjacent blocks. Moreover, it exploits the context across bit-planes to save side information. To improve subjective quality, our SBR reorders the coefficient bits by their estimated rate-distortion performance. Particularly, we model transform coefficients with Laplacian distributions and incorporate them into the context probability models for content-aware parameter estimation. Moreover, our SBR is implemented with a dynamic priority management that uses a low-complexity dynamic memory organization. Experimental results show that our CABIC improves the PSNR by 0.5 similar to 1.0 dB at medium and high bit rates. While maintaining similar or even higher coding efficiency, our SBR improves the subjective quality.
A filter-based self-similar trace synthesizer
(2007-05-01)
Yao, Chien
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Hua, Kai-Lung
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Chen, Po-Ning
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Chen, Jin-Yuan
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Chiang, Tihao
Recent empirical studies have shown that modern computer network traffic is much more appropriately modelled by long-range dependent self-similar processes than traditional short-range dependent processes such as Poisson. Thus, if its selfsimilar nature is not considered in the synthesis of experimental network data, incorrect performance assessments for network systems may result. This raises the need of a self-similar trace synthesizing algorithm with long-range dependence. In this paper, we propose and examine the feasibility of a filter-based method for the synthesis of self-similar network traces. The proposed approach can alleviate the problems encountered by conventional synthesizers, such as random midpoint displacement and Paxson's spectrum fitting, which cannot generate self-similar traces on the fly and may give negative numbers. Additionally, the extended range of self-similarity of the filtered approach can be easily managed by the filter truncation window; therefore, a trace that faithfully matches the measured behavior of true network traffic, where the self-similar nature only lasts beyond a certain range but disappears as the considered aggregated window is much further extended, can be generated.
A Low-Power and Bandwidth-Efficient Motion Estimation IP Core Design Using Binary Search
(2009-05-01)
Wang, Shih-Hao
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Tai, Shih-Hsin
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Chiang, Tihao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new architecture design for motion estimation using binary matching criterion is proposed to achieve low power and bus bandwidth efficiency. Low power and high bus bandwidth efficiency are the two key issues for portable video applications. To address such issues, we first study an efficient algorithm called all binary motion estimation (ABME), and analyze its architecture issues in operational flow and bus access. Then, we propose an architecture for ABME with four new features: 1) macroblock level pre-processing; 2) efficient binary pyramid search structure; 3) parallel processing of 8 x 8 and 16 x 16 block searches; 4) parallel processing of bi-directional search. Such architecture leads to a superior performance in bus access, speed, and power. Our experiments show that the power consumption is as low as 763 mu W for IPPPP CIF 30 frames/s and 896 mu W for IPBPB CIF 30 frames/s. The bus bandwidth savings are 54.3% for P-frame search and 67.1% for B-frame search.
A multiple-window video embedding transcoder based on H.264/AVC standard
(2007)
Li, Chih-Hung
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Wang, Chung-Neng
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Chiang, Tihao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a low-complexity multiple-window video embedding transcoder (MW-VET) based on H.264/ AVC standard for various applications that require video embedding services including picture-in-picture ( PIP), multichannel mosaic, screensplit, pay-per-view, channel browsing, commercials and logo insertion, and other visual information embedding services. The MW-VET embeds multiple foreground pictures at macroblock-aligned positions. It improves the transcoding speed with three block level adaptive techniques including slice group based transcoding (SGT), reduced frame memory transcoder (RFMT), and syntax level bypassing (SLB). The SGT utilizes prediction from the slice-aligned data partitions in the original bitstreams such that the transcoder simply merges the bitstreams by parsing. When the prediction comes from the newly covered area without slice-group data partitions, the pixels at the affected macroblocks are transcoded with the RFMT based on the concept of partial reencoding to minimize the number of refined blocks. The RFMT employs motion vector remapping (MVR) and intra mode switching (IMS) to handle intercoded blocks and intracoded blocks, respectively. The pixels outside the macroblocks that are affected by newly covered reference frame are transcoded by the SLB. Experimental results show that, as compared to the cascaded pixel domain transcoder (CPDT) with the highest complexity, our MW-VET can significantly reduce the processing complexity by 25 times and retain the rate-distortion performance close to the CPDT. At certain bit rates, the MW-VET can achieve up to 1.5 dB quality improvement in peak signal-to-noise-ratio (PSNR). Copyright (C) 2007 Chih-Hung Li et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
A NMR optimized bitrate transcoder for MPEG-2/4 LC-AAC
(2007)
Lai, Te-Hsueh
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Wang, Chung-Neng
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Chiang, Tihao
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交大名義發表
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National Chiao Tung University
This paper presents a noise-to-making-ratio (NMR) optimized MPEG-2/4 AAC Low-Complexity (LC) transcoder, called as Fast Rate-Distortion Optimized Transcoder (FRDOT). The FRDOT searches for the optimal scalefactors under the NMR criterion according to the magnitudes of quantized input coefficients and the target bitrate. The computation of NMR difference is replaced by the derivation of signal-to-noise-ratio (SNR) difference since the audible masking thresholds of the original and transcoded bitstreams are identical. The SNR value is further converted to a noise-to-signal-ratio (NSR) to represent distortion energy of audio signals. With the NSR values, a table lookup technique is used to speed up the search of the optimal scalefactor increment. To further reduce the execution time, a bandwidth limiter is used to remove the iterative rate-distortion optimization of a frame. In addition, a bitrate control module is proposed to make the averaged bitrate of output bitstream close to the target bitrate. The results show that the FRDOT has smaller NMR values than the cascaded transcoder (CT) by 0.5-3.0 dB at different bitrates with 6-7 times speedup on the average.
A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis
(2008)
Li, Chih-Hung
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Peng, Wen-Hsiao
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Chiang, Tihao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a system architecture for H.264/AVC video embedding transcoder (VET). In addition, the proposed platform-based design can seamlessly combine the MW-VET and decoder such that it can be dynamically configured to perform video decoding and transcoding alternatively or simultaneously. Furthermore, we perform the pruned design space exploration on the design of inter/intra prediction and the on-chip data bus width. Our proposed architecture provides a better tradeoff among execution cycles, hardware cost, resource utilization, and video quality because of the reconfigurable processing modules and the hybrid pipelining. As compared to the cascaded pixel domain transcoder that has the highest complexity, our hardware efficient VET can significantly reduce the hardware cost while maintaining similar rate-distortion performance. Finally, the proposed architecture is verified at system level using transaction level modeling (TLM) technique. From the simulation results, the proposed architecture with the best tradeoff configuration can achieve a transcoding rate up to 358 frames per second for SD video source while clocking at 162MHz.
Adding selective enhancement in scalable video coding for region-of-interest functionality
(2006)
Peng, Wen-Hsiao
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Chiang, Tihao
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Hang, Hsueh-Ming
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交大名義發表
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National Chiao Tung University
In this paper, we propose a lossless, graceful, and arbitrary-shaped region-of-interest (ROI) functionality for the scalable video coding in MPEG-4 Part 10 Amd. 1. Specifically, we propose a prioritized block coding scheme and a layer remapping technique. Within an enhancement layer, the prioritized block coding reshuffles the transform coefficients for ROI. Moreover, the layer remapping technique prioritizes different ROI among enhancement layers. For graceful and arbitrary-shaped properties, additional syntax are coded at the levels of slice, layer, and macroblock. To minimize overhead, an efficient representation for priority information is proposed. Experimental results show that our schemes can offer the ROI functionality over a wide range of bit rates while maintaining coding efficiency.
Advances in the scalable amendment of H.264/AVC
(2007-01-01)
Huang, Hsiang-Chun
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Peng, Wen-Hsiao
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Chiang, Tihao
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Hang, Hsueh-Ming
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交大名義發表
To support clients with diverse capabilities, ISO/IEC MPEG and ITU-T form a Joint Video Team (JVT) to develop a scalable video coding (SVC) technology that uses single bitstream to provide multiple spatial, temporal, and quality (SNR) resolutions, thus satisfying low-complexity and low-delay constraints. It is an amendment of the emerging standard H.264/AVC and it provides an H.264/AVC-compatible base layer and a fully scalable enhancement layer, which can be truncated and extracted on-the-fly to obtain a preferred spatio-temporal and quality resolution. An overview of the adopted key technologies in the SVC and a comparison in coding efficiency with H.264/AVC are presented.
Architecture for stack robust fine granularity scalability
(2005-09-08)
Huang, Hsiang-Chun
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Wang, Chung-Neng
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Chiang, Tihao
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Hang, Hsuch-Ming
The present invention relates to an architecture for stack robust fine granularity scalability (SRFGS), more particularly, SRFGS providing simultaneously temporal scalability and SNR scalability. SRFGS first simplifies the RFGS temporal prediction architecture and then generalizes the prediction concept as the following: the quantization error of the previous layer can be inter-predicted by the reconstructed image in the previous time instance of the same layer. With this concept, the RFGS architecture can be extended to multiple layers that forming a stack to improve the temporal prediction efficiency. SRFGS can be optimized at several operating points to fit the requirements of various applications while the fine granularity and error robustness of RFGS are still remained. The experiment results show that SRFGS can improve the performance of RFGS by 0.4 to 3.0 dB in PSNR.
Content-aware adaptive media playout controls for wireless video streaming
(2007-10-01)
Chuang, Hsiao-Chiang
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Huang, ChingYao
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Chiang, Tihao
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電控工程研究所
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Institute of Electrical and Control Engineering
Video streaming is one of the killer applications for cellular communications. The MPEG-4 fine-granularity scalability video coding technique can adapt to bandwidth variation and random packet errors. In this paper, to explore the impacts of cellular channel characteristics on the tolerance of buffer performance and quality of service, a novel statistical model-based adaptive media playout (AMP) is proposed by utilizing the statistical assumptions of both arrival and departure processes for a better decision on the dynamic threshold adjustment an frame-rate adjustment. Based on third-generation cellular transmission environment, simulation results will demonstrate that as compared to other AMP schemes, the proposed AMP control provides better visual quality with lower complexity.
Cross-layer mobile WiMAX MAC designs for the H.264/AVC scalable video coding
(2010-01-01)
Juan, Hung-Hui
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Huang, Hsiang-Chun
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Huang, ChingYao
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Chiang, Tihao
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電子工程學系及電子研究所
To effectively provide the QoS of streaming services in mobile WiMAX systems. this paper proposes it cross-layer design between the streaming server and mobile WiMAX base stations. We will show that for each user the Implementation Of Multiple connections with feedback Information of the available transmission bandwidth is critical for supporting H.264/AVC-based scalable video coding in which the transmission packets call be further separated into multiple levels of importance. To quantify the performance, a mobile WiMAX simulation platform including both the video encoder/decoder and IEEE 802.16e MAC controls is developed.
Design of memory sub-system in H.264/AVC decoder
(2007)
Li, Chih-Hung
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Chang, Chang-Hsuan
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Peng, Wen-Hsiao
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Hwang, Wei
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Chiang, Tihao
In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency; less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.
Design of memory sub-system with constant-rate bumping process for H.264/AVC decoder
(2007-02-01)
Li, Chih-Hung
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Peng, Wen-Hsiao
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Chiang, Tihao
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資訊工程學系
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電子工程學系及電子研究所
In this paper, we propose an efficient memory sub-system and a constant-rate bumping process for a H.264/AVC decoder conforming to High profile@ Level 4. To efficiently utilize the throughput of external DRAM a synchronization buffer is employed as a bridge for reformatting the read/write data exchanged between the on-chip hardware and the off-chip DRAM In addition, we optimize the issues of read/write commands and adaptively enable the auto-precharge function by monitoring the motion information of a submacroblock. Furthermore, a regulation buffer with size comparable to the decoded picture buffer is created to ensure a constant output rate of decoded pictures for any conformed prediction structures. Along with other modules, the proposed scheme is verified at system level using transaction level modeling (TLM) technique. Statistical results show that synchronization buffer of larger block size provides higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.
DESIGN SPACE EXPLORATION OF AN H.264/AVC-BASED VIDEO EMBEDDING TRANSCODER USING TRANSACTION LEVEL MODELING
(2008)
Li, Chih-Hung
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Peng, Wen-Hsiao
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Chiang, Tihao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we perform the design space exploration for an H.264/AVC video embedding transcoder. Specifically, the design space is pruned for the sub-modules including inverse transform, inter and intra. prediction, and deblocking filter with various microarchitecture designs, processing order, memory hierarchy, and granularity of synchronization. In addition, we propose an efficient deblocking filter suitable for 8x8 block pipeline. Compared to the traditional designs, our proposed deblocking filter reduces memory requirement, processing latency, and access frequency to the local memory. The synthesized logic gate count is only 8K using the 0.18 um technology with the maximum frequency of 162 MHz. For rapid exploration, all the design alternatives are simulated with higher level of abstraction using the transaction level modeling to explore 160 design combinations. Our simulation results provide an extensive tradeoff analysis among processing speed, cost, and utilization. Besides, the cost-normalized hardware utilization where the cost of each sub-module weights its associated utilization assists the system designers to keep a balance across different modules.
Fast motion estimation using N-queen pixel decimation
(2003-07-03)
Chiang, Tihao
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Liu, Chi-Min
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Wang, Chung-Neng
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Yang, Shin-Wei
The present invention proposes a fast motion estimation using N-queen pixel decimation, whereby after a reference block and a block to be processed are selected in a video sequence, an N×N queens pattern is used for pixel decimation to perform block match, thereby obtaining a good enough block difference value. The present invention combines pixel decimation with fast motion estimation for search points reduction to achieve the object of simplifying computational complexity of motion estimation. Therefore, the present invention can sieve out sufficiently representative pixels and will not increase extra computational complexity.
Method and apparatus for interframe wavelet video coding
(2005-09-15)
Tsai, Sam S.
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Hang, Hsueh-Ming
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Tsai, Chia-Yang
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Chiang, Tihao
The present invention provides a method and apparatus for interframe wavelet video coding which comprises Motion Compensated Temporal Filtering and Discrete Wavelet Transform Coding to obtain: 1. compressed quantification error and scalability on temporal analysis and spatial analysis, and 2. scalability on Motion Information (MI) data so that the performance of wavelet video coding on low bitrate can be improved. A method for partitioned coding on MI is proposed: 1. to partitioned coding a motion vector according to the spatial block, the temporal frame, or the numeric precision; 2. to partition motion vectors to a plurality of layers, and, when the video bitstream changes, only the required MI is put into the final bitstream. Accordingly, the performance of wavelet video compression on low bitrate is greatly improved while the compression rate on high bitrate is only a little lower.
Method for performing context adaptive binary arithmetic coding with stochastic bit reshuffling for fine granularity scalability
(2007-03-29)
Peng, Wen-Hsiao
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Chiang, Tihao
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Hang, Hsueh-Ming
The disclosure relates to a method for performing context based binary arithmetic coding with a stochastic bit-reshuffling scheme in order to improve MPEG-4 fine granularity scalability (FGS) based bit-plane coding. The method comprises steps of: replacing 8×8 DCT with 4×4 integer transform coefficient in MPEG-4 AVC (Advance Video-Coding); partitioning each transform coefficient into significant bit and refinement bit; setting up significant bit context based on energy distribution within a transform block and spatial correlation in adjacent blocks; using an estimated Laplacian distribution to derive coding probability for the refinement bit; and using the context across bit-planes to partition each significant bit-plane for saving side information bit.
Scalable video streaming over mobile WiMAX
(2007)
Juan, Hung-Hui
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Huang, Hsiang-Chun
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Huang, ChingYao
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Chiang, Tihao
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電子工程學系及電子研究所
In this paper, we will investigate the performance of scalable video streaming services in mobile WiMAX systems. We will show that for each user the implementation of multiple connections with feedback information of the available transmission bandwidth is critical for supporting H.264/AVC-based scalable video streaming in which the transmission packets can be further separated into multiple levels of importance. Based on a mobile WiMAX simulation platform including both the video encoder/decoder server and IEEE 802.16e MAC controls, the MAC performance evaluation and subjective test are used to quantify the visual performance between two-connection and one-connection scenarios.
Stack robust fine granularity scalable video coding
(2006-11-01)
Huang, Hsiang-Chun
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Chiang, Tihao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel scalable video coding technique, namely Stack Robust Fine Granularity Scalability (SRFGS), is presented to provide both temporal and SNR scalability. The SRFGS first simplifies the temporal prediction architecture of RFGS. The approach is further generalized using a reconstructed frame from the previous time instance of the same layer to temporally predict the quantization error of the lower layer. With this concept, the RFGS architecture can be extended to multi-layer stack architecture. The SRFGS can be optimized at several operating points to meet the requirements of various applications, while maintaining the fine granularity and error robustness of RFGS. An optimized macroblock-based alpha adaptation scheme is proposed to improve the coding efficiency. A single-loop enhancement layer decoding scheme is proposed to reduce the decoder complexity. The simulation results show that SRFGS can improve the performance of RFGS by 0.4 to 3.0 dB in PSNR. SRFGS has been reviewed by the MPEG committee and ranked as one of the best algorithms according to subjective testing in the Report on Call for Evidence on Scalable Video Coding.