Browsing by Author "Chiang, Tsung-Hsi"

Now showing 1 - 5 of 5

A VLSI progressive coding for wavelet-based image compression
(2007-05-01)
Chiang, Tsung-Hsi
;
Dung, Lan-Rong
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a new algorithm for progressive image coding, called Tag Setting In Hierarchical Tree (TSIHT). The TSIHT coding can save the memory requirement while keeping the low-bit-rate quality high. The TSIHT algorithm has been implemented onto a chip with 0.35 mu IP4M CMOS technology. The chip can handle 256x256 gray-scale images and the gate count is about 2560 gates within 247500 mu m2 area. The latency of the critical path is 6.32 ns, and the maximum working frequency can be as high as 158 MHz.(1)
High-quality image compression for gastrointestinal endoscope
(2007)
Dung, Lan-Rong
;
Chiang, Tsung-Hsi
;
交大名義發表
;
National Chiao Tung University
This paper proposes an efficient framework of high-quality image compression method for upper Gastrointestinal tract endoscopy images. The proposed DEWC coding method saves traditional image preprocessing computations, such as demosaicking and color-space transformation, and directly utilizes raw image data acquired from CMOS sensor. X G and B band image are then separately encoded by wavelet-based SPECK coding. In a cardinal GI tract environment, the spatial frequency distribution of red component is lower than green or blue, and green component is relatively high while compared to blue and red components. DEWC coding saves more bits on red band while allocating more bits on green and blue bands. Therefore, under a fixed compression ratio, such non-uniform bit-rate allocation may earn a better image quality. To measure quality-loss in non-uniform bit-rate allocation, a quality quantified measurement called color-distortion based on CIEE94 color-difference formula is also proposed. By using analytical result of color-distortion in bit-rate and bit-rate-difference analysis, an optimal/suboptimal bit-rate allocation scheme can be found by solving linear equations derived from the relationship of color-distortion and bit-rate-difference. When comparing to general JPEG2000 compression standard, the experimental result shows that proposed DEWC coding has a better image quality in color-distortion measurement and more efficient performance in execution time.
System-level veri cation on high-level synthesis of dataflow graph
(2006)
Chiang, Tsung-Hsi
;
Dung, Lan-Rong
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a system-level veri cation algorithm,,using the Petri Net theory to detect design errors for high-level synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optitrial scheduling. How to verify the correctness of highlevel synthesis becomes a key issue before mapping the synthesis results onto a silicon. Many tools exist for RTL design, but few for high-Revel synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the synthesis result. Herein, we propose three approaches to realize the Petri Net based formal veri cation algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage.
Verification method of dataflow algorithms in high-level synthesis
(2007-08-01)
Chiang, Tsung-Hsi
;
Dung, Lan-Rong
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a formal verification algorithm using the Petri Net theory to detect design errors for high-level synthesis of dataflow algorithms. Typically, given a dataflow algorithm and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto a silicon. Many tools exist for RTL (Register Transfer Level) design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the synthesis result, because the Petri Net model has the nature of dataflow algorithms. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and conclude the best one who outperforms the others in terms of processing speed and resource usage. (C) 2006 Elsevier Inc. All rights reserved.
VERIFICATION OF DATAFLOW SCHEDULING
(2008-09-01)
Chiang, Tsung-Hsi
;
Dung, Lan-Rong
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate process or resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level designor DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.