Browsing by Author "Chiang, Tsung-Yu"

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A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals
(2010-11-01)
Chiang, Tsung-Yu
;
Ma, William Cheng-Yu
;
Wu, Yi-Hong
;
Wang, Kuan-Ti
;
Chao, Tien-Sheng
In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is 10(-7) A by the band-to-band tunneling current. A much larger memory window (> 12 V) and good data retention time (> 10(8) s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications.
Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism
(2010-04-01)
Liao, Chia-Chun
;
Chiang, Tsung-Yu
;
Lin, Min-Chen
;
Chao, Tien-Sheng
;
電子物理學系
In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should bemodulated from the point of view of stress shift rather than using the highest tensile film.
Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors
(2011-04-01)
Ma, William Cheng-Yu
;
Chiang, Tsung-Yu
;
Yeh, Chi-Ruei
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility mu FE, rising from 14.33 to 22.33 cm(2)/V . s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility mu FE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified.
Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface Treatment
(2008-12-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO(2) gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO(2)/poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO(2) LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO(2) gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors
(2011-11-01)
Liao, Chia-Chun
;
Lin, Min-Chen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
電子物理學系
SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to explain the double-hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed not only to radical passivation of the defect states but also to radical passivation of preexisting defects in the gate oxide. Furthermore, using SiN passivation layers improves immunity to positive gate bias stress, negative gate bias stress, and hot-carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes.
Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-kappa Eu2O3 gate dielectrics
(2012-04-23)
Yen, Li-Chen
;
Hu, Chia-Wei
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Pan, Tung-Ming
In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-kappa Eu2O3 LTPS-TFT annealed at 500 degrees C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm(2)/V-s, a small subthreshold swing of 142 mV/decade, and a high I-on/I-off current ratio of 1.34 x 10(7). These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4705472]
Electrical Characteristics of High Performance SPC and MILC p-Channel LTPS-TFT with High-kappa Gate Dielectric
(2009)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Yeh, Chi-Ruei
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this article, high performance p-channel, low temperature polysilicon thin-film transistors (LTPS-TFTs) are fabricated by using HfO(2) gate dielectric and two crystallization methods, solid phase crystallization (SPC) and metal-induced lateral crystallization (MILC) are compared. High field-effect mobility mu(FE) 114 and 215 cm(2)/V s), ultralow subthreshold swing (SS similar to 145 and 107 mV/decade), and low threshold voltage (V(th) similar to -1.05 and -0.75 V) are derived from SPC- and MILC-TFTs with HfO(2) gate dielectric, respectively. These excellent electrical characteristics are due to low trap states and much higher gate capacitance density with equivalent oxide thickness similar to 12.3 nm, resulting in lower operation voltage within 2 V of LTPS-TFT without any passivation method. The comparison of SPC and MILC p-channel LTPS-TFTs with HfO(2) gate dielectric is demonstrated. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3177277] All rights reserved.
High-performance p-channel LTPS-TFT using HfO(2) gate dielectric and nitrogen ion implantation
(2009-07-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
;
電子物理學系
In this communication, a high-performance p-channel low-temperature poly-Si thin-film transistor with HfO(2) gate dielectric and nitrogen ion implantation is demonstrated for the first time. A low threshold voltage V(TH) = -0.8 V, excellent subthreshold swing S.S. = 0.123 V/decade, high field effect mobility mu(FE) = 64.14 cm(2) V(-1) s(-1) and high driving current I(Dsat) = 9.14 mu A mu m(-1) @ 3 V operation voltage of the p-channel LTPS-TFT can be achieved. The high performance characteristics are attributed to the very low effective oxide thickness EOT = 8.4 nm provided by the HfO(2) gate dielectric and the passivation of effective interface states and grain boundary traps by the nitrogen ion implantation treatment. It would be very suitable for the application of a high-speed and low-power pixel-driving device in flat-panel displays.
High-performance p-channel LTPS-TFT using HfO2 gate dielectric and nitrogen ion implantation
(2009-07-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
;
電子物理學系
In this communication, a high-performance p-channel low-temperature poly-Si thin-film transistor with HfO2 gate dielectric and nitrogen ion implantation is demonstrated for the first time. A low threshold voltage V-TH = -0.8 V, excellent subthreshold swing S.S. = 0.123 V/decade, high field effect mobility mu(FE) = 64.14 cm(2) V-1 s(-1) and high driving current I-Dsat = 9.14 mu A mu m(-1) @ 3 V operation voltage of the p-channel LTPS-TFT can be achieved. The high performance characteristics are attributed to the very low effective oxide thickness EOT = 8.4 nm provided by the HfO2 gate dielectric and the passivation of effective interface states and grain boundary traps by the nitrogen ion implantation treatment. It would be very suitable for the application of a high-speed and low-power pixel-driving device in flat-panel displays.
High-program/erase-speed SONOS with in situ silicon nanocrystals
(2008-10-01)
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
Wu, Yi-Hong
;
Yang, Wen-Luh
;
電子物理學系
In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 10(8) s for 13% charge loss).
High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method
(2009-06-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
A. high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I(PGM)) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.
Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Technique
(2011)
Liao, Chia-Chun
;
Lin, Min-Chen
;
Chiang, Tsung-Yu
;
Chao, Tien-Sheng
;
電子物理學系
This paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3506399] All rights reserved.
Impacts of N-2 and NH3 Plasma Surface Treatments on High-Performance LTPS-TFT With High-kappa Gate Dielectric
(2008-11-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Lei, Tan-Fu
Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high-kappa gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility mu(FE) improvements of similar to 86.0% and 112.5% are observed for LTPS-TFTs with HfO2 gate dielectric after N-2 and NH3 plasma surface treatments, respectively. In addition, the N2 and NH3 plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility mu(FE) at high gate bias voltage V-G, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage V-TH similar to 0.33 V, excellent subthreshold swing S.S. similar to 0.156 V/decade, and high field-effect mobility mu(FE) similar to 62.02 cm(2) /V . s would be suitable for the application of system-on-panel.
Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC
(2013-08-01)
Chen, Yi-Hsuan
;
Yen, Li-Chen
;
Chang, Tien-Shun
;
Chiang, Tsung-Yu
;
Kuo, Po-Yi
It is known that metal-induced lateral crystallization (MILC) thin-film transistors (TFTs) exhibit higher on-state current, steeper subthreshold slope, and lower minimum leakage than solid-phase-crystallization TFTs. In this letter, we propose a tunneling TFT (T-TFT) fabricated by MILC method for the first time. The MILC T-TFTs demonstrate a lower subthreshold swing, similar to 232 mV/decade, than the other T-TFTs and a high ON/OFF ratio > 10(6) at V-DS = 1 V without any hydrogen-related plasma treatment. These improvements can be due to the reduction of defects at grain boundaries and the channel direction parallel to grains. The polycrystalline silicon T-TFTs fabricated in this letter show a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays, and 3-D integrated circuits applications in the future.
MILC-TFT With High-kappa Dielectrics for One-Time-Programmable Memory Application
(2009-09-01)
Chiang, Tsung-Yu
;
Ma, Ming-Wen
;
Wu, Yi-Hong
;
Kuo, Po-Yi
;
Wang, Kuan-Ti
In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-cbannel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage V(th) similar to -0.78 V, excellent subthreshold swing similar to 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.
Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array
(2012-06-01)
Wang, Kuan-Ti
;
Hsueh, Fang-Chang
;
Lu, Yu-Lun
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 mu s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.
Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors
(2012-01-01)
Ma, William Cheng-Yu
;
Chiang, Tsung-Yu
;
Lin, Je-Wei
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S. S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/ decade and the threshold voltage V(TH) from 10.87 V to 5.00 V. Moreover, the threshold voltage V(TH) roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S. S. improvement due to a decreasing of the channel grain boundary trap density. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility mu(FE). Therefore, the channel length dependence of field-effect mobility mu(FE) is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.
Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash Memory
(2009-11-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Kuo, Po-Yi
For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR Flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (I(PGM)) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.