Browsing by Author "Chiao, WH"

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Low-power BIBITS encoding with register relabeling for instruction bus
(2005)
Cheng, CT
;
Chiao, WH
;
Shann, JJJ
;
Chung, CP
;
Chen, WF
Reducing power consumption of embedded system has gained much attention recently. Reducing memory bus switchings is an effective way to reduce system power since memory bus power constitutes a great portion of the system power. While many techniques exist for reducing bus power in address buses, only a few have been proposed for content-bus power reduction. We propose a Bus-Invert and Bus-Invert with transition signaling (BIBITS) encoding scheme to reduce power consumption on instruction bus. An instruction is partitioned into fields according to its format. Four elementary Boolean functions are used as encoding functions. BIBITS uses the most suitable encoding functions for different instruction partitions. We also propose a register relabeling algorithm for BIBITS encoding to further reduce bit switchings on register fields. Simulation results show that the overall average switching reduction is 64% of unencoded bus, 59% of the previous register relabeling scheme, and 33% of Petrov's bus encoding scheme. Compared with Petrov's bus encoding scheme, our scheme uses a decoding signal table only half the size to encode all basic blocks.
Low-power branch prediction
(2005)
Hu, YC
;
Chiao, WH
;
Shann, JJJ
;
Chung, CP
;
Chen, WF
Low-power design has gained much attention recently, especially for computing on battery-powered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we propose two approaches to reduce BTB accesses. The first approach expects the distance of every two dynamic branch instructions to be a constant n, where n can be statically profiled, and forces BTB to repose for n instructions after a BTB hit. The second approach dynamically predicts the address of the next branch instruction, and accesses BTB only on the predicted address. Multimedia/DSP benchmarks are used in our evaluation. Experimental results show that these methods can potentially reduce 22-033% of all BTB accesses.
Low-power data address bus encoding method
(2005)
Weng, TH
;
Chiao, WH
;
Shann, JJJ
;
Chung, CP
;
Lu, J
Reducing power consumption of computer systems has gained much research attention recently In a typical system, the memory bus power constitute will over 50% of all system power; and this power is required due to bus signal transitions (0 41 or 140). Reducing the number of memory bus transitions is hence an effective way to reduce system power While many techniques deal with reducing bus power on instruction address bus, only a few have been proposed for data address bus power reduction. We present an encoding scheme to reduce data address bus power consumption. In this scheme, data address bus can be frozen for sequential addresses, or inverted as appropriate for other cases. Furthermore, data addresses are classified info read addresses and write addresses, and each address set is encoded independently. Simulation results show that the overall bus line switching reduction is 26% of unencoded bus, or 14.5% of the previous T0_BI method [1].