Browsing by Author "Chien, CH"

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2-bit poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate
(2005)
Lin, YH
;
Chien, CH
;
Chou, TH
;
Chao, TS
;
Chang, CY
In this paper, we, for the first time, have successfully fabricated SONOS-type poly-Si-TFT memories employing three kinds of high-k dielectrics, including HfO(2), Hf-silicate and Zr-silicate, as the trapping layer with low-thermal budget processing. It was demonstrated that the fabricated memories exhibit good performance in terms of relatively large memory window, high program/erase speed (1ms/10ms), long retention time (> 10(6)S for 20% charge loss) and negligible read/write disturbances. In particular, 2-bit operation has been successfully demonstrated.
A model for photoresist-induced charging damage in ultra-thin gate oxides
(1997)
Lin, HC
;
Chien, CH
;
Wang, MF
;
Huang, TY
;
Chang, CY
The role of photoresist (PR) in affecting the gate oxide damage during plasma processing boas reexamined in this work. if was observed that, during the O-2 plasma ashing, more severe antenna effect may occur in devices with PR covering. A model is proposed to explain this phenomenon. This model considers the ability of plasma current injection through the substrate contacts, which are hindered by PR covering, to adjust the potential difference between gate electrode and substrate. We Sound that the presence of PR, antenna ratio, and gate-oxide thickness are all important parameters for charging damage effect.
A study of boron diffusion from selectively grown epitaxial silicon-germanium into silicon during rapid thermal annealing
(2002)
Yang, TH
;
Chang, EY
;
Chen, KM
;
Chien, CH
;
Huang, HJ
Boron diffusion from selectively grown epitaxial Si1-xGex into Si during rapid thermal annealing (RTA) was investigated. Selective epitaxial growth (SEG) of in-situ boron-doped strained Si1-xGex epitaxial layers with different Ge percentages were selectively grown by ultra high vacuum chemical molecular epitaxy (UHVCME). The results show that the boron diffusion depth from SEG Si1-xGex into n-type Si depends on boron concentration, Ge profile in the SEG area, and the size of the SEG area. Higher boron concentrations in SEG Si1-xGex film increases the boron diffusion depth. However, the diffusion depth can be reduced by increasing Ge composition in SEG Si1-xGex. It was also found that the samples with graded Ge profiles have higher diffusion depths than those with uniform profiles. In addition, the boron diffusion depth increases with the size of the SEG Si1-xGex area. The strain in SEG Si1-xGex, the chemical potential of Ge in SEG Si1-xGex and the dislocations induced in the SEG Si1-xGex layers are the main reasons for the phenomena observed.
An interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate
(2005-09-22)
Chen, SC
;
Lou, JC
;
Chien, CH
;
Liu, PT
;
Chang, TC
In this study, the hump in the capacitance-voltage (C-V) curves, variation of leakage current, interfacial layer increase, and electron trapping in non-surface treated hafnium oxide (HfO2) samples were observed and investigated. From the results of the investigation, it was found that both rapid thermal oxidation and NH3 surface treatments improved the C-V curves. In addition, it was observed that samples treated with ammonia exhibited a lower leakage current when compared with the others. From the results of the dielectric, leakage current study, a severe electron trapping effect was exhibited under higher electric field stress. Finally, the conduction mechanism in the HfO2 thin film was dominated by Frenkel-Poole emission in a high electric field. (c) 2005 Elsevier B.V All rights reserved.
Annealing temperature effect on the performance of nonvolatile HfO2Si-oxide-nitride-oxide-silicon-type flash memory
(2006-05-01)
Lin, YH
;
Chien, CH
;
Chang, CY
;
Lei, TF
;
電子工程學系及電子研究所
In this article, we demonstrate the effect of the postdeposition annealing for the HfO2 trapping layer on the performance of the Si-oxide-nitride-oxide-silicon-type flash memories. It was found that the memory window becomes larger while the retention and endurance characteristics get worse as the annealing temperature increases. This was ascribed to the larger amount and the shallower energy levels of the crystallization-induced traps as compared to the traps presented in the as-fabricated HfO2 film. Finally, in the aspect of disturbances, we show only insignificant read, drain, and gate disturbances presented in the three samples in the normal operation. (c) 2006 American Vacuum Society.
Bis(2,2-diphenylvinyl)spirobifluorene: An efficient and stable blue emitter for electroluminescence applications
(2005-08-15)
Wu, FI
;
Shu, CF
;
Wang, TT
;
Diau, EWG
;
Chien, CH
We have synthesized a spirobifluorene-based DPVBi [4,4'-bis(2,2-diphenylvinyl)-1,1'-biphenyl] analogue, DPVSBF [2,7-bis(2,2diphenylvinyl)-9,9'-spirobifluorene], in which the bis(2,2-diphenylvinyl) groups are connected through the 2 and 7 positions of the spirobifluorene framework, and have characterized its thermal properties, electronic properties (viz. absorption and photoluminescence), and electrochemical behavior. The presence of the rigid spirobifluorene linkage imparts significant improvement in the material's glass transition temperature and morphological stability, while preserving most of the photophysical and electronic properties of its non-spiro, biphenyl analogue, DPVBi. Organic electroluminescent devices having the structure ITO/NPB/DPVSBF/AlQ/LiF/Al display bright emissions with a lambda(max) at 474 nm (CIE coordinates: 0.16, 0.24) and exhibit maximum luminescence exceeding 40,000 cd/m(2). At a driving current density of 100 mAcm(2) (6.4 V), a luminance of 4110 cd/m(2) was obtained with external quantum efficiency of 2.54%, luminance efficiency of 4.1 cd/A, and power efficiency of 2.0 lm/W. Moreover, the DPVSBF-based device exhibits a 16-fold enhancement in the operation lifetime relative to that of a similar device based on DPVBi. (C) 2005 Elsevier B.V. All rights reserved.
Breakdown characteristics of ultra-thin gate oxides caused by plasma charging
(1999)
Chen, CC
;
Lin, HC
;
Chang, CY
;
Chien, CH
;
Huang, TY
Breakdown characteristics of ultra-thin gate oxides caused by plasma charging were studied in this work. It is observed that as oxide thickness is scaled down to 4 nn, some traditional monitor parameters may lose their sensitivity for detecting oxide degradation induced by plasma charging damage, due to insignificant trap generation. Even the gate leakage current, although sensitive for 4 nm oxide, may no longer be sensitive enough for even thinner oxide (e.g., 2.6 nm), due to the existence of large tunneling current. Moreover, several soft-breakdown events were found to occur in ultrathin oxide before the final onset of a catastrophic hard-breakdown. Finally, an equivalent local oxide thickness is calculated using local oxide thinning model to estimate the stepwise increase of gate current after soft-breakdown event.
Characteristics of the inter-poly Al(2)O(3) dielectrics on NH(3)-nitrided bottom poly-si for next-generation flash memories
(2005-04-01)
Chen, YY
;
Chien, CH
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of surface NH(3) nitridation of the bottom poly-Si film, and post-deposition annealing (PDA) temperature, on the electrical properties and reliability characteristics of aluminum oxide (Al(2)O(3)) inter-poly capacitors, were evaluated in this study. The polarity-dependent dielectric properties of Al(2)O(3) inter-poly dielectrics (IPDs) were strongly affected by both surface nitridation and the annealing temperature. For positive gate bias, IPDs with NH(3) surface nitridation significantly suppressed the formation of an additional layer with a lower dielectric constant, during the post-annealing process, and obtained a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si-N layer made the PDA more effective in eliminating the traps existing in the as-deposited films, and improved dielectric characteristics, under negative polarity. As a result, the smoother interface and smaller electron trapping rate contributed to the drastically reduced leakage current, enhanced breakdown field, and charge to breakdown (Q(bd)) of the Al(2)O(3) inter-poly capacitors with surface NH(3) nitridation. Moreover, the electrical properties of Al(2)O(3) IPD were heavily dependent upon the PDA temperature. The sample exhibited optimal quality in terms of leakage current, electron trapping rate and Qbd when annealed at 900 degrees C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from various compositions, under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining IPD electrical properties.
Characteristics of the inter-poly Al2O3 dielectrics on NH3-nitrided bottom poly-si for next-generation flash memories
(2005-04-01)
Chen, YY
;
Chien, CH
;
Lou, JC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of surface NH3 nitridation of the bottom poly-Si film, and post-deposition annealing (PDA) temperature, on the electrical properties and reliability characteristics of aluminum oxide (Al2O3) inter-poly capacitors, were evaluated in this study. The polarity-dependent dielectric properties of Al2O3 inter-poly dielectrics (IPDs) were strongly affected by both surface nitridation and the annealing temperature. For positive gate bias, IPDs with NH3 surface nitridation significantly suppressed the formation of an additional layer with a lower dielectric constant, during the post-annealing process, and obtained a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si-N layer made the PDA more effective in eliminating the traps existing in the as-deposited films, and improved dielectric characteristics, under negative polarity. As a result, the smoother interface and smaller electron trapping rate contributed to the drastically reduced leakage current, enhanced breakdown field, and charge to breakdown (Q(bd)) of the Al2O3 inter-poly capacitors with surface NH3 nitridation. Moreover, the electrical properties of Al2O3 IPD were heavily dependent upon the PDA temperature. The sample exhibited optimal quality in terms of leakage current, electron trapping rate and Qbd when annealed at 900 degrees C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from various compositions, under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining IPD electrical properties.
Characterization of antenna effect by nondestructive gate current measurement
(1996-08-15)
Lin, HC
;
Chien, CH
;
Huang, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel method is proposed for the effective characterization of plasma-charge-induced damage on thin gate oxides. We have found that the gate current measured at V-g(gate voltage) = V-th(threshold voltage) under a low drain bias (e.g., 0.1 V) is a good indicator of the damage. Since the proposed method requires only low bias voltages, it does not cause additional damage to the devices. The proposed gate current measurement is also easy to incorporate to device measurement routines without an extra stressing step, and thus provides a simple and efficient damage indicator for studying plasma-charge-induced damage.
Characterization of antenna effect by nondestructive gate current measurement
(1996-08-15)
Lin, HC
;
Chien, CH
;
Huang, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel method is proposed for the effective characterization of plasma-charge-induced damage on thin gate oxides. We have found that the gate current measured at V-g(gate voltage) = V-th(threshold voltage) under a low drain bias (e.g., 0.1 V) is a good indicator of the damage. Since the proposed method requires only low bias voltages, it does not cause additional damage to the devices. The proposed gate current measurement is also easy to incorporate to device measurement routines without an extra stressing step, and thus provides a simple and efficient damage indicator for studying plasma-charge-induced damage.
Deep sub-micron strained Si0.85Ge0.15 channel p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultra-thin N2O-annealed SiN gate dielectric
(2005)
Chen, CW
;
Chien, CH
;
Chen, YC
;
Hsu, SL
;
Chang, CY
We have investigated the electrical characteristics of strained Si0.85Ge0.15 channel p-channel metal-oxide-semiconductor field effect transistors (pMOSFETs) with ultra-thin N2O-annealed SiN gate dielectric. We have found that the thickness of SiGe channel has a great impact on the device characteristics. With controlling the SiGe layer thickness thinner than 15 nm, the device depict a subthreshold swing of 68 mV/A, the interface state density of 1 x 10(11) eV(-1) cm(-2), acceptable junction leakage, and more than 50% hole mobility improvement with respect to the Si channel device. Therefore, high quality interface between the gate dielectric and the strained SiGe channel can be achieved by using the N2O-annealed SiN gate dielectric.
Effects of low-temperature NH3 treatment on the characteristics of HfO2/SiO2 gate stack
(2005)
Lu, WT
;
Chien, CH
;
Huang, IJ
;
Yang, MJ
;
Lehnen, P
The effects of postdeposition low- temperature (400 degrees C) NH3 treatment (LTN treatment) on the characteristics of the HfO2/ SiO2 gate stack with the TiN gate electrode were studied in this work. After the HfO2 films were deposited using an AIXTRON Tricent atomic vapor deposition system, the LTN treatment was performed prior to the postdeposition annealing (PDA) step to prevent the growth of an additional interfacial layer, which is known to accompany the traditional high- temperature nitridation technique. The effective electrical oxide thickness for the devices annealed at 700 C PDA, either with or without LTN treatment, was estimated to be about 2.2 and 2.3 nm, respectively, without considering quantum effects. It was found that the LTN treatment effectively improves the characteristics of the HfO2/ SiO2 stack gates, such as capacitance- voltage (C-V) characteristics, frequency dispersion, trap generation rate, and dielectric breakdown voltage even at the high PDA temperature of 700 C. (c) 2005 The Electrochemical Society.
Effects of polysilicon gate doping concentration on plasma charging damage in ultrathin gate oxides
(2000-02-01)
Chen, CC
;
Lin, HC
;
Chang, CY
;
Huang, TY
;
Chien, CH
Effects of poly-gate doping concentration on plasma charging damage in ultrathin gate oxides were investigated. While the charge-to-breakdown (Q(bd)) value under gate injection stress polarity (-V-g) is independent of the doping concentration, eb, under substrate injection stress polarity (+V-g) shows a noticeable improvement with increasing doping concentration. However, our results show that plasma-induced oxide degradation is actually aggravated with increasing poly-gate doping concentration. These seemingly inconsistent observations can be explained by the lowering of plasma charging potential in the case of insufficient poly-gate doping. (C) 1999 The Electrochemical Society. S1099-0062(99)10-079-8. All rights reserved.
Effects of postdeposition annealing on the characteristics of HfOxNy dielectrics on germanium and silicon substrates
(2006)
Cheng, CC
;
Chien, CH
;
Chen, CW
;
Hsu, SL
;
Yang, CH
We have systematically investigated the impact that postdeposition annealing (PDA) has on the physical and electrical properties of HfOxNy thin films sputtered on Ge and Si substrates. These two substrates display contrasting metal-oxide-semiconductor characteristics that we attribute to the different compositions of their interface layers (ILs). We observed an increased GeO2 incorporation into the HfOxNy dielectric and severe volatilization of the IL on Ge after higher PDA processing. These undesired phenomena in the HfOxNy/Ge gate stacks may be responsible for their different electrical properties with respect to those of the HfOxNy/Si gate stacks, i.e., a further scaling of the capacitance-equivalent thickness, a significant presence of fixed positive charges and electron-trapping sites, and a degradation of dielectric reliability. In addition, the anomalous low-frequency-like behavior of the high-frequency capacitance-voltage curves in inversion for the Ge capacitors was predicted from theoretical calculations. (c) 2006 The Electrochemical Society.
Efficient sub-nanosecond intracavity optical parametric oscillator pumped with a passively Q-switched Nd : GdVO4 laser
(2004-11-01)
Chen, YF
;
Chen, SW
;
Tsai, LY
;
Chen, YC
;
Chien, CH
An efficient diode-pumped passively Q-switched Nd:GdVO4/Cr4+:YAG laser was employed to generate a high-repetition-rate, high-peak-power eye-safe laser beam with an intracavity optical parametric oscillator (OPO) based on a KTP crystal. The conversion efficiency for the average power is 8.3% from pump diode input to OPO signal output and the slope efficiency is up to 10%. At an incident pump power of 14.5 W, the compact intracavity OPO cavity, operating at 46 kHz, produces average powers at 1571 nm up to 1.2 W with a pulse width as short as 700 ps.
Electrical characteristics of thin cerium oxide film on silicon substrate by reactive DC sputtering
(2001-09-01)
Pan, TM
;
Chien, CH
;
Lei, TF
;
Chao, TS
;
Huang, TY
Electrical proper-ties of CeO2 films prepared by reactive dc sputtering on Si(100) substrate with and without the incorporation of a thin barrier layer were investigated. X-ray diffraction spectra revealed that without the thin barrier layer, single-crystal CeO2 is formed on Si(100) substrate. At an equivalent oxide thickness of 2.8 nm, CeO2 films exhibit a leakage current which is four orders of magnitude lower than that of the conventional SiO2 film at an applied bias of 2 V. Only negligible stress-induced leakage current is observed after high field stressing. The incorporation of the thin silicon nitride buffer layer, however, degraded the crystalline structure of CeO2, accompanied by deteriorated electrical properties such as leakage current and fixed charges. CeO2 film without the barrier layer is thus attractive as the high dielectric constant gate insulator for future ultralarge scale integration devices. (C) 2001 The Electrochemical Society.
Electrical characteristics of thin HfO(2) gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH(3) surface nitridation (NH(3)-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO(2) gate dielectrics. The NH(3)-annealed technique is superior to the others because the dielectric subject to NH(3) surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V(inv)), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(R(v)V(inv),). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
Electrical characteristics of thin HfO2 gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH3 surface nitridation (NH3-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO2 gate dielectrics. The NH3-annealed technique is superior to the others because the dielectric subject to NH3 surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V-inv), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(RvVinv,). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
Electrical properties of metal-ferroelectric-insulator-semiconductor using sol-gel derived SrBi2Ta2O9 film and ultra-thin Si3N4 buffer layer
(2002-12-02)
Huang, CH
;
Tseng, TY
;
Chien, CH
;
Yang, MJ
;
Leu, CC
The electrical properties of the metal-ferroelectric-insulator-silicon memories with stacked gate configuration of Pt/ SrBi2Ta2O9 (SBT)/Si3N4/p-Si (1 0 0) were investigated. In an attempt to operate at low voltage with sufficient large memory window, various ultra-thin Si3N4 buffer layers in thickness of 3.5, 2, and 0.9 nm were employed. From the results of C-V measurements, the memory window can be as large as 0.8 V at the bias amplitude of 5 V for the sample with 0.9 nm SixNy buffer layer. Well-crystallized perovskite structures have been further confirmed by the spectra of X-ray diffraction measurements. The leakage current, which plays a very important role in the data retention, of Pt/SBT (245 nm)/Si3N4 (0.9 nm)/p-Si (10 0) can be as low as 2.5 X 10(-8) A/cm(2) at 200 kV/cm. Excellent fatigue-free performance with up to 10(10) read/write cycles and good retention time of > 2 h have been obtained. Optimization and scaling of SBT thin films are believed to be effective in pursuing extremely low voltage operation, high-density and liable 1T nonvolatile ferroelectric random access memories. (C) 2002 Elsevier Science B.V. All rights reserved.