Browsing by Author "Chien, Cheng-An"

Now showing 1 - 9 of 9

3D DEPTH MAP GENERATION FOR EMBEDDED STEREO APPLICATIONS
(2012)
Lee, Jui-Sheng
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Jian, Guo-An
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Chien, Cheng-An
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Chen, Peng-Sheng
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Guo, Jiun-In
This paper presents a low complexity 3D image depth map generation algorithm for embedded stereo applications. The proposed algorithm generates depth information based on a single view 2D image automatically. Owing to different scene characteristics of image, we propose a mechanism to classify images to "Scenery", "Normal" and "Close-up" types first and generate the associated depth map according to the proposed techniques. In addition, we propose a human detection method for strengthening the depth information in images with humans and post-processing for refining depth map. With good quality in the generated depth map, the proposed algorithm achieves about 93% in complexity reduction as compared to the traditional algorithm, which is suitable for realization in both the hardware and embedded systems for portable stereo applications.
A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A Two level Mode Decision Algorithm for H.264 High Profile Intra Encoding
(2012)
Chang, Cheng-Yen
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Chien, Cheng-An
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Chang, Hsiu-Cheng
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Chen, Jia-Wei
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Guo, Jiun-In
A two level mode decision algorithm considering edge information for H.264 high profile intra encoding is proposed to reduce the computational complexity. In level one mode decision, the edge information is used to decide the appropriate intra coding block size according to the observations that a smooth macroblock usually chooses the large intra coding block size, and that a complex macroblock usually chooses the small one. In level two mode decision, we use the correlation between adjacent blocks to decide the appropriate prediction modes. The propose method achieves 34%similar to 59% reduction of computational complexity when compared to JM14 and the PSNR only drops 0.09 db in averag.
A Verification-Aware Design Methodology for Thread Pipelining Parallelization
(2012-10-01)
Jian, Guo-An
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Chien, Cheng-An
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Chen, Peng-Sheng
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Guo, Jiun-In
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電子工程學系及電子研究所
This paper proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively.
A VIEW SCALABLE MULTI-VIEW VIDEO DECODER SYSTEM
(2013-01-01)
Lee, Jui-Sheng
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Miao, Yuan-Hsiang
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Chien, Cheng-An
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Chang, Hsiu-Cheng
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Guo, Jiun-In
This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.
A VIEW SCALABLE MULTI-VIEW VIDEO DECODER SYSTEM
(2013)
Lee, Jui-Sheng
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Miao, Yuan-Hsiang
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Chien, Cheng-An
;
Chang, Hsiu-Cheng
;
Guo, Jiun-In
This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.
An Inter-frame/Inter-view Cache Architecture Design for Multi-view Video Decoders
(2012)
Lee, Jui-Sheng
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Wang, Sheng-Han
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Chou, Chih-Tai
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Chien, Cheng-An
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Chang, Hsiu-Cheng
In this paper we propose a low-bandwidth two-level inter-frame/ inter-view cache architecture for a view scalable multi-view video decoder, which adopts two decoder cores to decode multi-view videos in parallel. The first level L1 cache is developed for the single video decoder core, which is able to reduce 60% bandwidth in doing inter-frame prediction in average. Moreover, we develop the second level L2 cache architecture to reuse the same reference data for doing interview prediction among different decoder cores, which can further reduce 35% bandwidth. By adopting the proposed two-level cache architecture for doing inter-frame/ inter-view prediction, we can reduce 80% bandwidth through a view scalable multi-view video decoder implementation, which achieves real-time HD1080 dual-view video decoding.
High Efficiency Data Access System Architecture for Deblocking Filter Supporting Multiple Video Coding Standards
(2012-05-01)
Chien, Cheng-An
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Jian, Guo-An
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Chang, Hsiu-Cheng
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Chen, Kuan-Hung
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Guo, Jiun-In
"This paper presents an efficient VLSI architecture of in-loop deblocking filter (ILF) with high efficiency data access system for supporting multiple video coding standards including H. 264 BP/MP/HP, SVC, MVC, AVS, and VC-1. Advanced standards, such as H. 264 MP/HP, SVC, and MVC, adopt Macro Block Adaptive Frame Field (MBAFF) to enhance coding efficiency which results in the performance bottleneck of deblocking filter due to complex data access requirement. This design challenge has not been discussed in previous works according to our best knowledge. Therefore, we develop a Prediction Data Management (PDM) to manage the input prediction data order of deblocking filter for different coding types (like frame/field) and multiple standards. We also design an extended output frame buffer module to solve the system bus architecture restriction (like 1K boundary and burst length) and achieve high efficiency data access by using MB-based scan order. By using these techniques, we can solve the data accessing design challenge and reduce 67% bus latency. After being implemented by using 90 nm CMOS technology, the proposed work can achieve real-time performance requirement of QFHD (3840x2160@30fps) when operated at 156MHz at the cost of 50.6K gates and 2.4K bytes local memory. The maximum operating frequency of the proposed design, i.e. 370MHz, is higher than the required real-time operating frequency so that voltage scaling may be adopted to reduce power consumption."
Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization
(2013-07-01)
Jian, Guo-An
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Chien, Cheng-An
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Chen, Peng-Sheng
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Guo, Jiun-In
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電子工程學系及電子研究所
We propose a low-complexity algorithm for stereoscopic video applications that generates a high-quality 3D image depth map from a single 2D image. Based on their characteristics, 2D images are classified into one of three categories before being processed by the proposed low-complexity algorithm to generate corresponding depth maps. We also extend the 3D depth algorithm to construct a parallel 3D video system. A thread-level superscalar-pipelining approach is developed to parallelize the 3D video system. Experimental results for HD1080 resolution images demonstrate that the algorithm can generate high-quality depth maps with an average reduction in the computational complexity of 98.2 % compared with a conventional algorithm. The parallel 3D video system can achieve a processing speed of 63.66 fps for HD720 resolution video.