Browsing by Author "Chien, Feng-Tso"

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A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Yu, Ming H.
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Wu, Chun-Yu
;
Kang, Tsung-Kuei
A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.
A novel self-aligned field induced drain polycrystalline silicon thin film transistor fabricated by using a selective side etch process
(2007)
Liao, Ta-Chuan
;
Wu, Chun-Yu
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Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has maximum on-off current ratio of 4.6 x 10(7), and off-state leakage current at V-GS = -10 V and V-DS = 5V of about 100 times less than that of the conventional one. These improvements are attributed to the additional undoped offset region and the vacuum gap, which reduce the maximum electric field at drain junction while the sub-gate maintains the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).
A poly-Si thin-film transistor with the in situ vacuum gaps under the T-shaped-gated electrode
(2006)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A T-shaped-gated (T-gate) poly-Si thin-film transistor (TFT) with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics. (c) 2006 The Electrochemical Society.
Advanced gate-all-around fin-like poly-Si TFTs with multiple nanowire channels
(2008)
Tu, Shih-Wei
;
Liao, Ta-Chuan
;
Lin, Wei-Kai
;
Liu, Cheng-Chin
;
Tai, Ya-Hsiang
The gate-all-around (GAA) fin-like poly-Si TFTs (FinTFTs) with multiple nanowire channels (MNCs) have been fabricated using a simple process to demonstrate high performance electrical characteristics. The fin-like nanowire (NW) channel with high body thickness-to-width ratio (T-Fin/W-Fin), approximately equals to one, was realized only with a sidewall-spacer formation. The unique suspending MNCs were also achieved to build the GAA structure. By the way, the GAA-MNC Fin TFTs showed outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (>10(8)), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering and a good reliability. Therefore, such the high-performance GAA-MNC FinTFTs are vet-v suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.
Improving electrical performance of the scaled low-temperature poly-Si thin film transistors using vacuum encapsulation technique
(2008)
Lin, Wei-Kai
;
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Tu, Shih-Wei
;
Liu, Yen-Ting
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain Junction..