Browsing by Author "Chien, Meng-Wei"

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A Dynamic Bootstrap Voltage Technique for a High-Efficiency Buck Converter in a Universal Serial Bus Power Delivery Device
(2016-04-01)
Chen, Wei-Chung
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Chou, Ying-Wei
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Chien, Meng-Wei
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Chen, Hsin-Chieh
;
Yang, Shang-Hsien
The dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over wide ranges of load currents for high-power universal serial bus devices. The silicon area of the embedded power management with the DBV technique in the system-on-a-chip can be effectively reduced to 50% of the conventional design with a P-type high-side power MOSFET. Test chips fabricated in 0.25-mu m CMOS process showed a 92% peak efficiency from 1 mA to 1 A. The maximum driving current was higher than 5 A, and the efficiencywas 88%. Compared with the efficiency of the converter without the DBV technique, the efficiency of the converter with DBV technique was improved by about 28%.
A Low THD Clock-Free Class-D Audio Amplifier with an Increased Damping Resistor and Cross Offset Cancellation Technique
(2014-01-01)
Chou, Ying-Wei
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Chien, Meng-Wei
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Chen, Shin-Chieh
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Chen, Ke-Horng
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Lin, Ying-Hsi
an increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8 Omega load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).
Anti-ESL/ESR Variation Robust Constant-on-time Control for DC-DC Buck Converter in 28nm CMOS Technology
(2014-01-01)
Chen, Hsin-Chieh
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Chen, Wei-Chung
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Chou, Ying-Wei
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Chien, Meng-Wei
;
Wey, Chin-Long
Conventional constant-on-time (COT) control for DC-DC buck converter is apt to be affected by the noise caused by parasitic effect including not properly specified and temperature dependent equivalent series resistance (ESR) and equivalent series inductance (ESL). As a result, the safety operation area (SOA) of the COT is limited by the selection of external components. In this paper, the calibrated anti-ESL (CAESL) technique and the calibrated gain and BW (CGB) technique for alleviating ESL and ESR variation, respectively, are proposed to ensure a robust COT control. Furthermore, degraded output regulation caused by enlarged ESL effect due to input battery voltage variation is also solved by the CAESL technique. The proposed COT converter fabricated in 28nm CMOS technology uses an output capacitor with an ESR smaller than 1m Omega, output ripple of 20mV, and high efficiency higher than 95%. The CAESL circuit can tolerate ESL voltage variation from 0 to 50mV even when operation temperature varies from -40 to 120 degrees C.
Pseudo AC Current Synthesizer and DC Offset-Corrected Technique in Constant-on-time Control Buck Converter for Werable Electronics
(2015)
Su, Jui-Che
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Chen, Wei-Chung
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Lin, Wei-Tin
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Chou, Ying-Wei
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Chien, Meng-Wei
Constant-on-time (COT) control with an additional current feedback in conventional buck converter has the advantage of using low equivalent series resistance (ESR) output capacitor. Unfortunately, the disadvantage is output voltage regulation accuracy is greatly deteriorated by its DC offset voltage from the current feedback. More seriously, opposite reaction between output voltage and the additional current feedback signal deteriorates transient response. In this paper, pseudo AC current synthesizer and DC voltage offset correction technique are proposed to reduce load-dependent DC offset voltage for improving load regulation. Furthermore, the transient enhancement technique instantly extends on-time and the off-time periods in load change. Test chip fabricated in UMC 28nm CMOS process demonstrated that offset voltage is improved from 65mV to 4mV. Besides, the transient response can be improved to 4 mu s and 5 mu s when load changes from 0.3 to 1.7A and vice versa, respectively. The advantages of compact size, low cost, and high performance power management can maintain wearable electronics small volume, light, and sustainable.
Pseudo-Constant Switching Frequency in On-Time Controlled Buck Converter with Predicting Correction Techniques
(2016-05-01)
Chen, Wei-Chung
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Chen, Hsin-Chieh
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Chien, Meng-Wei
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Chou, Ying-Wei
;
Chen, Ke-Horng
The predicting correction technique (PCT) is proposed to achieve an adaptive on-time control for ripple-based buck converters. The switching frequency f(SW) variation is suppressed when the PCT technique considers complete parasitic resistances of the components and devices. Even without extra clock-controlled circuits and current sensing circuits, the buck converter operates with a nearly constant f(SW) over a wide load range. Parasitic resistances almost cause no influence and restriction on f(SW). Only input voltage is used to predict the adaptive on-time. Measurement results show only 0.32% in Delta f(SW) / f(SW) and 5.7 kHz/A in Delta f(SW) / Delta I-LOAD in case of 1.4 A load current change and f(SW) is 2.5 MHz. Consequently, a pseudo-constant f(SW) with well-defined noise spectrum strongly benefits the solution of electromagnetic interference (EMI) for system-on-a-chip (SoC) applications.
Suppressing Output Overshoot Voltage Technique with 47.1mW/mu s Power-Recycling Rate and 93% Peak Efficiency DC-DC Converter for Multi-core Processors
(2015)
Chien, Meng-Wei
;
Yang, Wen-Hau
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Chou, Ying-Wei
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Chen, Hsin-Chieh
;
Chen, Wei-Chung
Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/mu s ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and high-speed operation with only tens of nano second on-time period.