Browsing by Author "Chien, SC"

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A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering
(2005)
Chung, SS
;
Liu, YR
;
Wu, SJ
;
Lai, CS
;
Liu, YC
In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC(Hot Carrier) and NBT (Negative Bias Temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (I I 0)/(l 00) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/(100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices.
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
(2002)
Chung, SS
;
Chen, SJ
;
Yang, CK
;
Cheng, SM
;
Lin, SH
For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.
Comparison of oxide breakdown progression in ultra-thin oxide SOI and bulk pMOSFETs
(2004)
Chan, CT
;
Kuo, CH
;
Tang, CJ
;
Chen, MC
;
Wang, TH
Accelerated oxide breakdown progression in ultra-thin oxide (1.4nm) SOI pMOSFETs is observed, as compared to bulk devices. The accelerated progression is explained by the increase of hole stress current as a result of breakdown induced channel carrier heating in a floating-body configuration. Numerical simulation of hole tunneling current and hot carrier luminescence measurement are carried out to justify the proposed theory.
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
(2004)
Chung, SS
;
Feng, HJ
;
Hsieh, YS
;
Liu, A
;
Lin, WM
A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Angstrom-16Angstrom range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate detennination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.
Low RF loss and noise of transmission lines on Si substrates using an improved ion implantation process
(2003)
Chan, KT
;
Chin, A
;
McAlister, SP
;
Chang, CY
;
Tseng, C
Very low power loss less than or equal to 0.6 dB at 110 GHz and noise of < 0.25 dB at 18 GHz have been measured on transmission lines fabricated on Si substrates and implanted with proton. In contrast, much worse power loss of 5 dB and higher noise of 2.5 dB were measured without implantation. This large improvement arises from the high resistivity by proton implantation, which was also done after forming the transmission lines and at a reduced energy of similar to 4 MeV for easier process integration into current VLSI technology.
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs
(2003)
Wang, TH
;
Tsai, CW
;
Chen, MC
;
Chan, CT
;
Chiang, HK
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.
Optimized noise and consistent RF model for 0.18 mu m MOSFETs
(2003)
Huang, CH
;
Li, HY
;
Chin, A
;
Liang, V
;
Chien, SC
Strong dependence of finger number on minimum noise figure (NFmin) is observed in 0.18 mum MOSFETs. A lowest NFmin of 0.93 dB is measured at 5.8 GHz using 50 fingers but increases as either increasing or decreasing finger number. We have used a self-consistent S-parameter and NFmin model to analysis this abnormal finger number dependence, and the reason is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number.
RF passive devices on Si with excellent performance close to ideal devices designed by electro-magnetic simulation
(2003)
Chin, A
;
Chan, KT
;
Huang, CH
;
Chen, C
;
Liang, V
High quality RF inductors, very low loss and noise CPW and microstrip lines, advanced broad and narrow band filters, and ring resonators have been achieved on Si substrates, using an optimized proton implantation process. The RF performance up to 100 GHz is close to that for ideal devices designed by EM simulation for lossless substrates.
Substrate-bias-dependent dielectric breakdown in ultrathin-oxide p-metal-oxide-semiconductor field-effect transistors
(2005-07-15)
Chiang, S
;
Lu, MF
;
Huang-Lu, S
;
Chien, SC
;
Wang, TH
An explanation of the breakdown behavior of ultrathin-gate-oxide (1.6 nm) p-metal-oxide-semiconductor field-effect transistors under a reverse substrate bias is presented. A significant degradation in lifetime induced by a positive substrate bias and a decrease in the power-law exponent (n) were observed. The quantitative hydrogen-based model [J. Sune and E. Wu, Digest of Technical Papers, 2001 Symposium on VLSI Technology, Kyoto, Japan, 12-14 June 2001 (unpublished), p. 97] is used to explain this observation while taking the channel quantization effect into consideration. Using this model, the stress voltage dependence of time-dependent dielectric breakdown in our experiment fits well with simulation results. This indicates that the degradation is due to the channel hole quantization-enhanced dissipation energy of injected electrons at the anode interface. (c) 2005 American Institute of Physics.
The minimum noise figure and mechanism as scaling RF MOSFETs from 0.18 to 0.13 mu m technology nodes
(2003)
Huang, CH
;
Chan, KT
;
Chen, CY
;
Chin, A
;
Huang, GW
As scaling down the RF MOSFET from 0.18 to 0.13 mum technology nodes, the f(T) increases but the NFmin becomes worse by increasing similar to0.2 dB. A small NFmin of 0.93 dB is measured at 5.8 GHz in 0.18 mum MOSFET using 50 fingers but increases as either increasing or decreasing finger number. This abnormal dependence and higher noise at 0.13 mum is accurately analyzed by equivalent circuit model and due to the combined gate resistance and substrate effect.