Browsing by Author "Chih, JC"

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A CORDIC processor with efficient table-lookup schemes for rotations & on-line scale factor compensations
(2005)
Chih, JC
;
Chen, KL
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we improve our previous efficient CORDIC processor design. The improvements consist of two parts: (1) an improved table-lookup rotation scheme with a smaller table than before, and (2) a new efficient on-line table-lookup scheme for scale-factor computations and compensations which is better than the previous non-online design. Combining the improvements with the original efficient rotation angle recoding algorithm and leading-one (or zero) bit detection (for skipping redundant rotations), we obtain a lowiteration and low-complexity COREDC processor architecture. The design is more efficient than the current designs, especially in the iteration count. Simulation shows that for n-bit results, about only n/4 iterations are required. We also designed a 16-bit CORDIC processor based on 0.25 mu m UMC process. Its averaged iteration count is only 4.4 including rotation and scale factor compensations, with a total gate count of 5742 and a maximum operating frequency of 250MHz.
A fast CORDIC algorithm based on a novel angle recoding scheme
(2000)
Chih, JC
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Chen, SG
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a new CORDIC algorithm, which considerably reduces rotation number. It is achieved by combining several design techniques. Particularly, a new angle recoding scheme for table lookup is developed to speed up the convergence rate of the rotation angle. The required lookup table is small. Other design techniques used include: the leading-one bit detection, the variable-scale-factor compensation algorithm [6]. The number of the shift-and-add operations required in the compensation algorithm can be also further reduced by using the same residue recoding scheme. Simulations show that in aver;ige the new design needs only 3.5; iterations to generate results with 22-bit precision, which is much less than the existing designs (normally need 22 iterations). The new encoding scheme can be applied to other iterative convergence computation function such as division operation.
An efficient direct digital frequency synthesizer based on two-level table lookup
(2001)
Chih, JC
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Chou, JY
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Chen, SG
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交大名義發表
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National Chiao Tung University
This paper proposes a new direct digital frequency synthesizer (DDFS). It has the merits of high speed, low complexity and high spectrum purity [1], [2]. It is based on the Taylor's expansion method for sinusoidal and cosine functions, combined with a two-level table-lookup algorithm. The new DDFS is efficient, with a small table size and low computational complexity. In all, this new DDFS needs three lookup tables, each of size 2(N/4), which is smaller than the other table-lookup methods, such as Madisetti, et al., (of size 2(N/3)) [3], [4]. The DDFS is non-recursive, which is free of error-propagation problem inherently in the recursive DDFS's. For N=16-bits example, simulation shows that the new DDFS has a high SFDR (spurious free dynamic range) of 100 dBc.
Fast CORDIC algorithm based on a new recoding scheme for rotation angles and variable scale factors
(2003-01-01)
Chih, JC
;
Chen, SG
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a new rotation mode CORDIC algorithm, which considerably reduces the iteration number. It is achieved by combining several design techniques. Particularly, a new table-lookup recoding scheme for rotation angles and variable scale factors is developed to reduce the iteration numbers for rotation and scale factor compensation. By addressing the MSB parts of the residual rotation angles to a lookup table, two micro rotation angles are retrieved that in combination best matches the MSB parts. We also combine the leading-one bit detection operations for residual rotation angles, to skip unnecessary rotations. The resulting problems of variable scale factors are then solved by our previous fast decomposition and compensation algorithm (C.C. Li and S. G. Chen, in Proceedings of 1996 IEEE International Symposium Circuits and Systems, May 1996, Atlanta, USA, pp. 264-267; C.C. Li and S.G. Chen, in Proceedings of 1997 IEEE International Conference on Acoustic, Speech and Signal Processing, Munich, 1997, Germany, pp. 639-642). To further reduce the iteration number of scale factor compensation, we again apply the mentioned residual recoding technique and the leading-one bit detection scheme to the fast variable scale factor algorithm. Those techniques collectively reduce the iteration number significantly. Simulations show that in average the new design needs only 9.78 iterations to generate results with 22-bit accuracy, including all the iterations for rotations and scale factor compensations. Statistically, the total iteration number is less than n/2 for results with n-bit accuracy. The introduced extra table size is of the same order of magnitude as that for the angle set {tan(-1) 2(-i), i = 0, 1,..., n}, required by general CORDIC algorithms. The new recoding scheme can be applied to other elementary function such as division and square-root functions.