Browsing by Author "Chih, Jen-Chuan"
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Item type:Item, Direct digital frequency synthesis based on a two-level table-lookup scheme(2006-12-01) ;Chen, Sau-Gee ;Chih, Jen-Chuan ;Chou, Jun-Yi ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsIn this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor's expansion. This method only needs a lookup-table size of total n x 2(n/4+1) + (n/4 - 2) x 2(n/4) bits, one (n + 1) x 3n/4-bit multiplier, one n x 3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS's, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 mu m cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.Item type:Item, Efficient CORDIC designs for multi-mode OFDM FFT(2006-01-01) ;Yu, Cheng-Ying ;Chen, Sau-Gee ;Chih, Jen-Chuan ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsIn this paper, we propose a new CORDIC algorithm and architectures which can generate close-to-optimum rotation sequences easily with small lookup table sizes. This new design is particularly suitable for the applications of adjustable-length FFT. In all, the required number of shift-and-add operations for micro-rotations and scale-factor compensations is only n/2, where n is the output precision. For design verification, we synthesized both serial and pipelined architectures, by using Synopsys Design Complier based on UMC 0.18 mu m, 1P6M CMOS technology. The synthesized 16-bit pipelined FFT PE runs at 222MHz, with a total gate count of 89263 and a low-power consumption of 26.75 mW It meets the FFT speed requirements of most OFDM-based communication systems, including DAB, DV-B, 802.16 and VDSL. Compared with a conventional multiplier-based FFT PE and the existing CORDIC-based FFT PE's, the proposed designs has better performances in terms of area, speed and power consumption.