Browsing by Author "Chin, Ching-Yu"

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A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
(2015-09-01)
Pan, Po-Cheng
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Chin, Ching-Yu
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Chen, Hung-Ming
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Chen, Tung-Chieh
;
Lee, Chin-Chieh
Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper first introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation. And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variable-gain amplifier, a folded-cascode operational amplifier, and a low dropout regulator. The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.
A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function
(2012)
Aroonsantidecha, Suradeth
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Liu, Sean Shih-Ying
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Chin, Ching-Yu
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
In this paper, we propose a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. Our thermal model is evaluated by the most recent commercial tool and has an average deviation of 6.5% with 242x speed up. Our placer can reach the same quality compared to Capo and APlace2 with 2-3x speed up. Experiments are tested using ISPD 2005 benchmark with up to 2 million gate design. The results are further evaluated using GSRC Bookshelf Evaluator for total HPWL, and using ICEPAK for temperature distribution. To the best of our knowledge, this is the first thermal-aware placer using analytical thermal model and experimented on large scale design. It takes 6.5 hours to complete entire 2005 ISPD benchmark using our thermal aware placer.
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
(2009)
Chin, Ching-Yu
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Tsou, Yao-Te
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Chang, Chi-Min
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Chao, Mango C. -T.
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電子工程學系及電子研究所
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package testing instead of in its wafer testing, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
(2011-12-01)
Chao, Mango C. -T.
;
Chin, Ching-Yu
;
Tsou, Yao-Te
;
Chang, Chi-Min
;
電子工程學系及電子研究所
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package test instead of in its wafer test, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing
(2017-01-01)
Wu, Wan-Ning
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Chen, Chen
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Chin, Ching-Yu
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Wang, Chun-Kai
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Chen, Hung-Ming
Packing and placement are two crucial stages for FPGA realization. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This work presents an analytical placement framework for heterogeneous FPGAs through a rough-placed packing algorithm. In the packing stage, we first perform a fast wirelength-driven placement for the basic logic units. With the physical information from the initial placement, we implement an affinity-based clustering algorithm while taking the control signal constraints into consideration. In the placement stage, a quadratic global placer is implemented with the techniques of handling the heterogeneity, routing congestion estimation and cell inflation. An incremental placer is performed after the global placement for closing the gap between the global placement and legalization, and a detailed placer is adopted to legalize the blocks and reduce the proposed methodologies can effectively improve the placement solutions.
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
(2014-11-01)
Wang, Chun-Kai
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Chang, Yeh-Chi
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Chen, Hung-Ming
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Chin, Ching-Yu
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電子工程學系及電子研究所
This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.
Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation
(2013)
Chin, Ching-Yu
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Pan, Po-Cheng
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Chen, Hung-Ming
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Chen, Tung-Chieh
;
Lin, Jou-Chun
To strive for better circuit performance on analog design, layout generation heavily relies on experienced analog designers' effort. Other than general analog constraints such as symmetry and wire-matching are commonly embraced in many proposed works, analog circuit performance is also sensitive to routing behavior. This paper presents a CDT-based layout extraction to preserve routing behavior of the reference layout. Furthermore, a generalized layout prototyping methodology is proposed based on the layout extraction to achieve routing reuse. The proposed layout prototyping is applied to a variable-gain amplifier and a folded-cascode operational amplifier for both migration and prototypes generation. Experimental results show that our approach effectively reduces design cycle time and simultaneously produces reasonable performance.
Escaped Boundary Pins Routing for High-Speed Boards
(2013-03-01)
Chin, Ching-Yu
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Kuan, Chung-Yi
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Tsai, Tsung-Ying
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Chen, Hung-Ming
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Kajitani, Yoji
Routing for high-speed boards is still achieved manually today. There have recently been some related works to solve this problem; however, a more practical problem has not been addressed. Usually, the packages or components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. In this paper, we describe this fixed ordering boundary pin routing problem, and propose a practical approach to solve it. Not only do we provide a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. Our approach has different features compared with the conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirements and wire shape resemblance for high-speed signal routes on board. Our results show that we can utilize routing resources very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board buses as well.
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function
(2014-06-01)
Liu, Sean Shih-Ying
;
Luo, Ren-Guo
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Aroonsantidecha, Suradeth
;
Chin, Ching-Yu
;
Chen, Hung-Ming
In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240x speedup.
Fault Models for Embedded-DRAM Macros
(2009)
Chao, Mango C. -T.
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Yang, Hao-Yu
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Huang, Rei-Fu
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Lin, Shih-Chin
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Chin, Ching-Yu
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.
Mathematical Yield Estimation for Two-Dimensional-Redundancy Memory Arrays
(2010)
Chao, Mango C. -T.
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Chin, Ching-Yu
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Lin, Chen-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an induction-based approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a time-consuming simulation to estimate the expected yield, our yield-estimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.
Mean-time-to-crack Model of Microbump Interconnect in FCGBA Package under Thermal Cyclic Test
(2013-01-01)
Chen, Chien-Chang
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Wu, Wei-Chen
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Chin, Ching-Yu
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Chen, Hung-Ming
;
Lin, Vito
By employing the physical characteristics of creep deformation mechanisms for solder joints in a flip-chip ball grid array (FCBGA) package under a thermal cyclic condition, an analytical model for the prediction of mean-time-to-crack (MTTC) is presented in the paper. With the consideration of time-dependent thermal testing functionals, the basic co-analyses of one-cycle Nabarro-Herring and Coble creep rates and the corresponding damage accumulation functionals for the conventional eutectic Sn/Pb micro-solder material are studied using the proposed MTTC model theoretically. For experimentally validation of the MTTC model, a batch of devices filled with resin in FCGBA package had been tested under a -40 degrees C similar to 125 degrees C thermal cyclic test with a period of 1-hour 1000 times. The MTTC model reveals that the solder bumps within the FCGBA can survive about 0.53 year under the cyclic testing circumstance. Under the room temperature, the device even can survive about 2.45 years under continuously operations.
On Routing Fixed Escaped Boundary Pins for High Speed Boards
(2011-01-01)
Tsai, Tsung-Ying
;
Lee, Ren-Jie
;
Chin, Ching-Yu
;
Kuan, Chung-Yi
;
Chen, Hung-Ming
Routing for high speed boards is still achieved manually nowadays. There have been some related works in escape routing to solve this problem recently, however a more practical problem is not addressed. Usually the pack-ages/components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. Previous works in escape routing are not likely to be used due to this nature, in this work, we describe this fixed ordering boundary pin escaping problem, and propose a practical approach to solve it. Not only can we have a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. our approach has different feature compared with conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirement and wire shape resemblance for high speed signal routes on board. Our results show that we can utilize routing resource very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board busses as well.
On Simultaneous Escape Routing of Length Matching Differential Signalings
(2013-01-01)
Lee, Yen-Jung
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Chen, Hung-Ming
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Chin, Ching-Yu
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In substrate or PCB design, the escape routing problem is considered an essential part and has been widely studied in literature. There are industrial tools and some studies that work on simultaneous escape routing and escape routing of differential pairs on dense circuit boards. However, to route differential pairs simultaneously considering length-matching is still an important and on-going research problem. In this work, inspired by prior state-of-the-arts, we have implemented an integrated approach that achieves simultaneous escape routing considering length matching of differential pairs, our method avoids time-consuming ILP solutions in finding length-matching differential signal paths. Experimental results show that our approach can efficiently and effectively obtain length-matching of differential pairs on simultaneous escape routing to reduce differential-pair skews, compared with B-escape router we reimplemented.
Simultaneous Escape Routing on Multiple Components for Dense PCBs
(2013-01-01)
Chin, Ching-Yu
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Simultaneous escape routing on dense boards is a very challenging task and lots of efforts have been spent. Most previous works focus on routing with one or two components, but in reality more components are possibly involved. In this paper, we propose a new simultaneous escape routing algorithm that considers multiple components at once. The proposed routing algorithm can solve simultaneous escape problem when two or more busses are connected to the same component. The experimental results show that, our routing algorithm can efficiently arrange escape paths properly to avoid net crossings and blockings between different busses.