Browsing by Author "Chin, LF"

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A comprehensive study on the FIBL of nanoscale MOSFETs
(2004-10-01)
Tsui, BY
;
Chin, LF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the I-off with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 run. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.