Browsing by Author "Chiou, SG"

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Resist-related damage on ultrathin gate oxide during plasma ashing
(1997-02-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Chiou, SG
This paper presents an important observation of plasma-induced damage on ultrathin oxides during O-2 plasma ashing by metal ''antenna'' structures with photoresist on top of the electrodes, It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10(4), In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging, This phenomenon is contrary to most previous reports, It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides.
Resist-related damage on ultrathin gate oxide during plasma ashing
(1997-02-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Chiou, SG
This paper presents an important observation of plasma-induced damage on ultrathin oxides during O-2 plasma ashing by metal ''antenna'' structures with photoresist on top of the electrodes, It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10(4), In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging, This phenomenon is contrary to most previous reports, It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides.
The role of a resist during O-2 plasma ashing and its impact on the reliability evaluation of ultrathin gate oxides
(1997-07-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Hsien, SK
Resists are regarded as protective layers for underlying devices during plasma ashing. In previous studies, resists were deliberately removed by a wet etching process prior to plasma exposure in an effort to achieve significant device degradation. In this paper we report that, contrary to conventional belief, devices with a resist overlayer actually suffer from more severe degradation than those without a resist covering. This resist-enhanced degradation effect, although not observed for devices with a thick gate oxide of 8 nm, becomes significant as the oxide thickness is scaled down below 6 nm. The most severe device degradation is found to be located at the center of the wafer and is found to increase with increasing antenna area ratio. Damage is also found to occur not during the overashing period, but primarily during the initial ashing stage when the resist is still on the electrodes. Using a combination of a simple equivalent capacitor circuit model and the self-adjustment behavior of potential between the wafer surface and substrate, good correlation with the experimental results is obtained.
The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
(1997-05-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chiou, SG
;
Huang, TY
During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.
The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
(1997-05-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chiou, SG
;
Huang, TY
During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.