Browsing by Author "Chiu, Chao-Chang"

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120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
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Chen, Jui-Lung
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Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
87% Overall High Efficiency and 11 mu A Ultra-Low Standby Current Derived by Overall Power Management in Laptops With Flexible Voltage Scaling and Dynamic Voltage Scaling Techniques
(2016-04-01)
Yang, Shang-Hsien
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Chen-Min
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Meng, Che-Hao
The proposed overall power management in laptops can improve overall power conversion efficiency by the flexible voltage scaling (FVS) technique in cooperation with conventional dynamic voltage scaling (DVS) technique. The FVS technique separates the controller into two parts. One is a simple primary side controller and the other is emerged into the power management unit in the laptop for getting direct power control from the microprocessor. 12% light load efficiency and 7% peak efficiency are improved compared to conventional design with the DVS technique only but without the FVS technique. Furthermore, green mode is proposed to effectively reduce chip quiescent current to 11 mu A and to suppress power loss to 10 m W in ultra-light load, which is much smaller than 500 mW standby power defined by the restriction of Energy Star Standard and 40 mW of state-of-art commercial products.
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement
(2015-01-01)
Chiu, Chao-Chang
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Huang, Po-Hsien
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Lin, Moris
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Chen, Ke-Horng
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Lin, Ying-Hsi
The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction
(2016-09)
Yang, Shang-Hsien
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Meng, Che-Hao
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Ke-Horng
A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the minimum total harmonic distortion (THD) achievable. By deriving a methodology to achieve predictive line voltage reconstruction (PLVR), the influence of the dead zone is mitigated. With the prediction of quadratic sinusoidal current modulation ((PSCM)-C-2), the line current is shaped into sinusoid waveform that is in-phase with input line voltage, crucial for. Consequently, the proposed CCM buck PFC can achieve high PF, low THD, and efficiency simultaneously. A test chip was fabricated in 0.5-mu m Bipolar-CMOS-DMOS (BCD) process. The experimental results show a peak PF of 0.95 and a peak efficiency of 98% at 110 Vac.
A Compact Power Management for Next Generation Intensive Care Unit with 91% Conversion Efficiency
(2014-01-01)
Chiu, Chao-Chang
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Yang, Hsiang-An
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Su, Yi-Ping
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Chang, Chih-Wei
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Meng, Che-Hao
the proposed single-inductor dual-output (SIDO) converter with energy-conservation mode (ECM) control is designed for next generation intensive care unit. The energy-conservation mode (ECM) control generates two different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. The measurement results shows the 91% peak efficiency can he derived.
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
(2013-04-01)
Lee, Yu-Huei
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Peng, Shen-Yu
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Chiu, Chao-Chang
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Wu, Alex Chun-Hsien
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Chen, Ke-Horng
A low quiescent current asynchronous digital-LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm(2) in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/mu s as well as the improved MIPS performance by 5.6 times was achieved.
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System
(2012-11-01)
Lee, Yu-Huei
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Chiu, Chao-Chang
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Peng, Shen-Yu
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Chen, Ke-Horng
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Lin, Ying-Hsi
A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm(2) silicon area. Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.
A Single-Inductor Bipolar-Output Converter with 5 mV Positive Voltage Ripple for Active Matrix OLED
(2011)
Chen, Wei-Chung
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Chiu, Chao-Chang
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5V and the negative output voltage is -7V for driving the AMOLED. When the load current is 25 mA and the ESR is 30m Omega, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50mA
A Single-Inductor Dual-Output Converter with Switchable Digital-or-Analog Low-Dropout Regulator for Ripple Suppression and High Efficiency Operation
(2012)
Lee, Yu-Huei
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Chen, Wei-Chung
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Chiu, Chao-Chang
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Peng, Shen-Yu
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Chu, Kuan-Yu
a single-inductor dual-output (SIDO) converter with the switchable digital-or-analog (D/A) low-dropout (LDO) regulator achieves an analog dynamic voltage scaling (ADVS) function for ripple suppression and high efficiency in system-on-achip (SoC). The ADVS function helps dynamically adjust the dropout voltage of the switchable D/A LDO regulator with analog operation for ripple suppression according to the load current. On other hand, the switchable D/A LDO regulator activates the digital operation for high efficiency at light loads since the dropout voltage of the LDO regulator can be further reduced. Besides, the bidirectional asynchronous signal pipeline (BASP) can realize the 50nA quiescent current in digital LDO regulator. This chip was fabricated by the 40 nm CMOS process. Experimental results demonstrate the switchable LDO regulator operation with the peak efficiency of 92% and the 7 mV output voltage ripple at 200 mA load because of the ripple suppression. The efficiency can be kept higher than 83% even the load current is 1 mA.
Authentic Mode-Toggled Detector with Fast Transient Response under Wide Load Range Buck-Boost Converter
(2013)
Lin, Moris
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Huang, Yung-Sheng
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Ehrhart, Andreas
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Lee, Yu-Huei
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Chiu, Chao-Chang
an authentic mode-toggled detector (AMTD) technique is proposed to achieve load and line regulations in a proposed buck-boost (BB) converter. In the case of load transient, conventional BB converter will oscillate and cannot settle to a well-regulated output voltage owing to the on-resistance of the power MOSFETs. Accurate and expeditious mode-toggled detection in the BB converter meet the requirements of load and line transient response by means of the proposed adaptively near-immediate freezer (ANIF) technique. Besides, due to pulse frequency modulation (PFM) implemented in the proposed BB converter, ultra wide load range from 10mA to 900mA can have high efficiency from 80% to 95%. Simulation results show the proposed BB converter fabricated in VIS 0.25 mu m process can be well-regulated under the input voltage ranging from 2.7V to 4.2V.
High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger
(2017-04-01)
Yang, Shang-Hsien
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Tsai, Tsung-Hsun
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Chen, Hsin
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Chiu, Chao-Chang
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Chen, Ke-Horng
In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltages due to switching, it also affect the resonance frequency which would reduce the timing of the sampling circuit, resulting in the inaccurate sampling of output voltage. By analyzing the snubber circuit and its resonance on the primary side, this paper implements a proposed accuracy knee voltage detection (AKVD) technique to compensate for the induced resonance frequency. Furthermore, the proposed constant current (CC) regulator ensures the accuracy of CC mode by compensating the sensing current error caused by the switching delay of the power transistor. A prototype consisting of a test chip fabricated with a 0.5 mu m BCD process demonstrates a voltage accuracy exceeding 99.63%. This is achieved by mitigating abnormal detections and thus ensuring correct control of charging current throughout the charging period.
High Efficiency and Total Harmonic Distortion Improvement by Zero Current Prediction Technique for Transformer-Free Buck Power Factor Corrector
(2014-01-01)
Meng, Che-Hao
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Chang, Chih-Wei
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Chiu, Chao-Chang
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Chen, Ke-Horng
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Lin, Ying-Hsi
Power factor correction (PFC) can shape the input current of off-line power supplies to be in-phase with the input AC voltage to maximize the available real power from the AC source for high power factor (PF). Boundary current mode (BCM) operation is the easiest way to get good power factor performance. However, the zero current detection in conventional PFC based on the voltage across the auxiliary winding which is suffer from the delay of zero current detection timing. Therefore, this paper proposed a high efficiency and total harmonic distortion (THD) improvement for transformer-free buck power factor corrector with zero current prediction mechanism. The chip fabricated in 0.5 mu m 800V ultra-high voltage (UHV) process can be powered on directly by the AC source owing to the 800V ultra-high voltage device. The output voltage of buck PFC is set at 80V and the PF is high to 0.98 without additional component compared with traditional buck PFC. The maximum efficiency of proposed buck PFC converter is 98.4% when input voltage is 110V AC.
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
(2013-11-01)
Peng, Shen-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Chiu, Chao-Chang
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Chen, Ke-Horng
This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-mu m standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/mu s saved 53% power.
Quasiresonant Control With a Dynamic Frequency Selector and Constant Current Startup Technique for 92% Peak Efficiency and 85% Light-Load Efficiency Flyback Converter
(2014-09-01)
Kang, Yu-Chai
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Chiu, Chao-Chang
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Lin, Moris
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Yeh, Chih-Pu
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Lin, Jinq-Min
The proposed quasiresonant control scheme can be widely used in a dc-dc flyback converter because it can achieve high efficiency with minimized external components. The proposed dynamic frequency selector improves conversion efficiency especially at light loads to meet the requirement of green power since the converter automatically switches to the discontinuous conduction mode for reducing the switching frequency and the switching power loss. Furthermore, low quiescent current can be guaranteed by the constant current startup circuit to further reduce power loss after the startup procedure. The test chip fabricated in VIS 0.5 mu m 500 V UHV process occupies an active silicon area of 3.6 mm(2). The peak efficiency can achieve 92% at load of 80 W and 85% efficiency at light load of 5W.
Self-Calibrated Knee Voltage Detector With 99.65% High Accuracy for AC Charger System in 0.5 mu m 500 V UHV Process
(2014-10-01)
Chiu, Chao-Chang
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Lin, Moris
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Chang, Chih-Wei
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Meng, Che-Hao
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Yang, Hsiang-An
The self-calibrated knee voltage detector (SC-KVD) for electrical isolation primary side charger applications is proposed. The removal of the feedback network which is used in conventional designs and occupies at least 30 mm(2) can save PCB area up to around 11%. Besides, the SC-KVD can dynamically adjust the detection point to improve the accuracy to 99.65% compared to the prior arts. The test chip fabricated in 0.5 mu m 500 V UHV process can be powered on directly by the AC source owing to the 500 V ultra-high voltage device. Hence, the battery charger can be made more compact and portable than it was and the battery life can be prolonged and guaranteed.