Browsing by Author "Chiu, JC"

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Decoding of CISC instructions in superscalar processors with high issue rate
(2000-03-01)
Shiu, RM
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Chiu, JC
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Cheng, SK
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Shann, JJJ
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資訊工程學系
The paper examines the design issues of decoders, including the primitive operation (POP) translation strategies and the decoding rules, for CISC superscalar processors to exploit a higher degree of parallel execution. Attention is focused on the x 86 instruction set because of its popularity. There are two different approaches regarding POP translation strategies: one is to merge the address generation into load/store operations, and the other is to translate the isolated address generation operations. Simulation results show that, in high issue-rate decoders, the latter strategy improves the performance by 20 to 25 %. Furthermore, considering the tradeoffs between the hardware cost and performance, a cost-effective decoding rule suitable for current commercial programs is recommended.
Design of instruction address queue for high degree x86 superscalar architectures
(2002-05-01)
Chiu, JC
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Wang, MJY
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Chung, CP
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資訊工程學系
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Department of Computer Science
A major hurdle of recent x86 superscalar processor designs is limited instruction issue rate due to the overly complex x86 instruction formats. To alleviate this problem, the machine states must be preserved and the instruction address routing paths must be simplified. We propose an instruction address queue, whose queue size has been estimated to handle saving of instruction addresses with three operations: allocation, access, and retirement. The instruction address queue will supply the stored instruction addresses as data for three mechanisms: changing instruction flow, updating BTB, and handling exceptions. It can also be used for internal snooping to solve self-modified code problems. Two CISC hazards in the x86 architectures, the variable instruction length and the complex addressing mode, have been considered in this design. Instead of the simple full associative storing method in lower degree (< 4) superscalar systems, the line-offset method is used in this address queue. This will reduce by 1/3 the storage space for a degree-5 superscalar x86 processor with even smaller access latency. We use synthesis tools to analyze the design, and show that it produces optimized results. Because the address queue design can keep two different line addresses in an instruction access per cycle, this method can be extended for designing a multiple instruction block issue system, such as the trace processor.
Design of instruction stream buffer with trace support for x86 processors
(2000)
Chiu, JC
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Huang, IH
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Chung, CP
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資訊工程學系
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Department of Computer Science
The potential performance of superscalar microprocessors can be exploited only when fed with sufficient instruction bandwidth. The front-end units, the instruction stream buffer and the fetcher, are the key elements achieving this goal. In most current processors, instruction stream buffers cannot support the instruction sequence beyond a basic block. The fetch rates ale constrained by the branch barriers. In x86 processors, the split-line instruction problem worsens this constraint. We propose a design to improve instruction stream buffer performance by coupling it with BTB to support trace prediction. According to the simulation results of such an instruction stream buffer; the maximum fetch bandwidth can reach 8.42 x86 instructions per cycle. Furthermore, we suggest that the instruction stream buffer consist of two 64-bytes entries. Compared with other existing designs, this instruction stream buffer can improve performance by 90% over current x86 processor instruction fetching on average.
High-bandwidth x86 instruction fetching based on instruction pointer table
(2001-05-01)
Chiu, JC
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Chung, CP
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資訊工程學系
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Department of Computer Science
Providing higher degree superscalar instruction fetching is a major concern in a high performance superscalar processor design. In x86 architectures, the variable-length instructions make fetching multiple instructions in a cycle difficult. A common practice is to use predecoded information to help in instruction fetching, while the complex instruction formats induce high redundancies in storing and processing the pre-decoded information in the cache. In the paper, the authors propose to use an Instruction Identifier to predict instruction length and store the instruction pointers as superscalar instruction group indicators. With this method, the difficulty of achieving a high instruction fetch degree (>3) can be overcome. Simulation results suggest that the Instruction Identifier with a 64-entry table is a good performance/cost choice. In the meantime, as the table size decreases, the prediction scheme becomes increasingly important. Moreover, simulation and circuit synthesis show that this design is feasible for high clock rate design.
Instruction cache prefetching directed by branch prediction
(1999-09-01)
Chiu, JC
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Shiu, RM
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Chi, SA
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Chung, CP
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資訊科學與工程研究所
As the gap between processor speed and memory speed grow, so the performance penalty of instruction cache misses gets higher. Instruction cache prefetching is a technique to reduce this penalty. The prefetching methods determine the target line to be prefetched generally based on the current fetched line address. However, as the cache line becomes wider, it may contain multiple branches. This is a hurdle which must be overcome. The authors have developed a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches, called branch instruction based (BIB) prefetching; in which the prefetch information is recorded in an extended BTB. Simulation results show that for commercial benchmarks, BIB prefetching outperforms traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average. As BTB designs become more sophisticated and achieve higher hit and accuracy ratios, BIB prefetching can achieve a higher level of performance.
Instruction cache prefetching with extended BTB
(1997)
Chi, SA
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Shiu, RM
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Chiu, JC
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Chang, SE
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Chung, CP
Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determines the target fine to be prefetched based on the current fetched fine address. However, as the cache fine becomes wider, there may be multiple branches in a cache fine which hurdles the decision made by these methods. This paper develops a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches. We call it the branch instruction based (BIB) prefetching, In BIB prefetching, the prefetch information is recorded in an extended BTB. Simulation results show that, the BIB prefetching outperforms the traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average, iis the BTB designs become more sophisticated and achieve higher hit and accuracy ratio the BIB prefetching can achieve higher performance.
Variable-size data item placement for load and storage balancing
(2003-05-15)
Ma, YC
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Chiu, JC
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Chen, TF
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Chung, CP
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資訊工程學系
The rapid growth of Internet brings the need for a low cost high performance file system. Two objectives are to be pursued in building such a large scale storage system on multiple disks: load balancing and storage minimization. We investigate the optimization problem of placing variable-size data items onto multiple disks with replication to achieve the two objectives. An approximate algorithm, called LSB Placement, is proposed for the optimization problem. The algorithm performs bin packing along with MMPacking to obtain a load balanced placement with near-optimal storage balancing. The key issue in deriving the algorithm is to find the optimal bin capacity for the bin packing to reduce storage cost. We derive the optimal bin capacity and prove that LSB Placement algorithm is asymptotically 1-optimal on storage balancing. That is, when the problem size exceeds certain threshold, the algorithm generates a load balanced placement in which the data sizes allocated on disks are almost balanced. We demonstrate that, for various Web applications, a load balanced placement can be generated with disk capacity not exceeding 10% more than the balanced storage space. This shows that the LSB Placement algorithm is useful in constructing a low cost and high performance storage system. (C) 2002 Elsevier Science Inc. All rights reserved.