Browsing by Author "Chiu, Kang-Lun"

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A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems
(2019-01-01)
Ng, Chee-Kit
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Chiu, Kang-Lun
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Lin, Yu-Chun
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Jou, Shyh-Jye
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電子工程學系及電子研究所
A 50Gb/s all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems is presented. Based on a parallel extended incremental coefficients-lookahead scheme (EICL), we propose a Dual Data-paths Self-Lookahead Filter (DD-SLF) for ADFE. DD-SLF architecture has better energy efficiency and hardware area than an original SLF architecture due to the number of delay elements in the feedback loop is reduced. Furthermore, gated clock technique with the design idea of register file architecture is used to replace the pipelined delay elements to save power. The whole equalizer which operates at 1GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a 0.38mm(2) core area. The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.
A 75-Gb/s/mm(2) and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm
(2020-04-01)
Lopez, Henry
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Chan, Hsun-Wei
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Chiu, Kang-Lun
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Tsai, Pei-Yun
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Jou, Shyh-Jye Jerry
This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10(-7)). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm(2), power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm(2) and 10.2 pJ/bit, respectively.
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications
(2019-01-01)
Chiu, Kang-Lun
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Chan, Hsun-Wei
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Lee, Wei-Che
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Wu, Chang-Ting
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Lopez, Henry
In this paper, we introduce a 10 Gbps digital baseband transceiver with IV supply voltage, 16-QAM, 3/4 code rate single carrier mode using 28 nm CMOS process to do the implementation. In millimeter wave communications, well-defined standard, IEEE 802.11ad is referenced for our system design and simulation. We target at modified chip rate 2.5 GHz with 4 times parallelism hardware at clock rate 625 MHz. The overall transceiver architecture design with hardware implementation considerations will be proposed. With the smart shared memory allocation, we can reduce 31% of the total amount. According to the referenced specifications, we achieve the required bit error rate 3 x 10(-7) before SNR 18.5 dB. After the system algorithm design, we implement the hardware with the core area 2.92 mm(2) with measured power 1.8 Watt for baseband transceiver chip. The performance of energ,y per bit is 0.023 nJ and 0.211 nJ per hit 6w Tx and Rx, including ADC/DAC.
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access
(2020-09-01)
Chiu, Kang-Lun
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Shen, Pai-Hsiang
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Lin, Bing-Ru
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Hsiao, Wei-Han
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Jou, Shyh-Jye Jerry
This work focuses on the design of downlink receiver for future generation cellular systems. In the multipath division multiple access (MDMA) system, the initial synchronization process includes timing and carrier frequency synchronization as well as home cell search. For the proposed system, the user data is transmitted in time domain and the cell search is based on control signals transmitted in frequency domain simultaneously. Firstly, this paper presents a novel architecture for the joint detection and estimation of both the coarse symbol boundary and the fractional carrier frequency offset based on cyclic prefix in time domain. Secondly, a robust integer carrier frequency offset detection is performed with the primary control tone in frequency domain. Moreover, the position of the secondary control tones is used to obtain the cell ID. Finally, the preamble sequence carried by the secondary control tones is used to detect frame header through differential detection. The simulation results show the proposed synchronization algorithms can achieve detection failure rate less than 1% and the normalized residual carrier frequency offset is less than 5% under the interference of user data. Furthermore, a hardware design targeted at 200 Mbps per-user data rate is realized with memory arbiter to share memory.