Browsing by Author "Chiu, Po-Yen"

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Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices
(2013-10-01)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
A new 2 x V-DD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1xV(DD) devices can successfully transmit and receive 2 x V-DD signal. Utilizing this technique with only 1xV(DD) devices, the digital logic gates are also modified to have 2xV(DD)-tolerant capability. With 2xV(DD)-tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from 2 x V-DD signal and provide compensation control to the 2 x V-DD-tolerant I/O buffer without suffering the gate-oxide overstress issue.
DESIGN OF 2xV(DD) LOGIC GATES WITH ONLY 1xV(DD) DEVICES IN NANOSCALE CMOS TECHNOLOGY
(2013-01-01)
Chiu, Po-Yen
;
Ker, Ming-Dou
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電機學院
;
College of Electrical and Computer Engineering
The novel 2xV(DD) NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1xV(DD) devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2xV(DD) tolerant capability. Thus, the new 2xV(DD) logic gates can be operated under 2xV(DD) voltage environment without suffering the gate-oxide reliability issue.
ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process
(2007)
Hsiao, Yuan-Wen
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Ker, Ming-Dou
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Chiu, Po-Yen
;
Huang, Chun
;
Tseng, Yuh-Kuang
The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz: frequency band. VVith the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.
ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
(2017-02)
Ker, Ming-Dou
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Chiu, Po-Yen
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Shieh, Wuu-Trong
;
Wang, Chun-Chi
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電子工程學系及電子研究所
Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of +/- 15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.
ESD-Induced Latchup-Like Failure in a Touch Panel Control IC
(2017-01-01)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
Shieh, Wuu-Trong
;
Wang, Chun-Chi
;
電子工程學系及電子研究所
With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD tests of HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin. The holding voltage of the power-rail ESD clamp circuit in the high-voltage power pin, that was lower than its normal operating voltage, caused such a latchup-like failure. Some modified solutions to rescue this latchup-like failure in the touch panel control IC are presented.
Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process
(2012)
Dai, Chia-Tsen
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Chiu, Po-Yen
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Ker, Ming-Dou
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Tsai, Fu-Yi
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Peng, Yan-Hua
The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
(2014-01-01)
Chiu, Po-Yen
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Between the metal-insulator-metal (MIM) capacitor and metal-oxide-metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnections, which does not need additional fabrication masks into the process. Moreover, the capacitance density of the MOM capacitor can exceed the MIM capacitor when more metal layers are used in nanoscale CMOS processes. With advantages of lower fabrication cost and higher capacitance density, the MOM capacitor could replace MIM capacitor gradually in general integrated circuit (IC) applications. Besides, the MOM capacitor ideally do not have the leakage issue. Thus, the MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes. With the MOM capacitor realized in the power-rail electrostatic discharge (ESD) clamp circuit, the overall leakage is decreased from 828 mu A to 358 nA at 25 degrees C, as compared to the traditional design with MOS capacitor in the test chip fabricated in a 65 nm CMOS process. (C) 2013 Elsevier Ltd. All rights reserved.
New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
(2011-09-01)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
電機學院
;
College of Electrical and Computer Engineering
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25 degrees C) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.
On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process
(2009)
Ker, Ming-Dou
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Chiu, Po-Yen
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Tsai, Fu-Yi
;
Chang, Yeong-Jar
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電子工程學系及電子研究所
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 degrees C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process
(2009)
Chiu, Po-Yen
;
Ker, Ming-Dou
;
Tsai, Fu-Yi
;
Chang, Yeong-Jar
;
電子工程學系及電子研究所
A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25 degrees C, which is much smaller than that (613 mu A) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.