Browsing by Author "Chiu Yi-Wei"

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SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION
(2013-08-01)
Jou Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Chiu Yi-Wei
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.
Single-ended SRAM with cross-point data-aware write operation
(2014-04-08)
Jou Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Chiu Yi-Wei
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.
Static memory and memory cell thereof
(2014-09-16)
Jou Shyh-Jye
;
Tu Ming-Hsien
;
Hu Yu-Hao
;
Chuang Ching-Te
;
Chiu Yi-Wei
A static memory and a static memory cell are provided. The static memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a first pull-down switch, and a second pull-down switch. When a data writing operation is performed, the latching capability of the latch circuit constituted by the first to the sixth transistors is disabled by turning off the second transistor or the fifth transistor, so that the speed of the data writing operation is increased and the data writing performance is improved. The first switch and the second switch provide a path for reading or writing data, and the third switch is coupled to a bit line for receiving data from or transmitting data to the bit line.