Browsing by Author "Cho, CYS"

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A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells
(2002-07-01)
Cho, CYS
;
Chen, MJ
;
Lin, JH
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Chen, CF
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電子工程學系及電子研究所
Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I-D = I-o exp[q(V-GB - nV(SB))/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients.
A novel self-aligned highly reliable sidewall split-gate flash memory
(2006-03-01)
Cho, CYS
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Chen, MJ
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Chen, CF
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Tuntasood, P
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Fan, DT
A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F-2 (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 105 confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250 degrees C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.
Fast and precise subthreshold slope method for extracting gate capacitive coupling coefficient in flash memory cells
(2003)
Cho, CYS
;
Chen, MJ
;
Chen, CF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A fast and precise subthreshold slope method for extraction of gate capacitive coupling coefficient is substantially confirmed by experimental data from three types of flash memory cells: stacked gate, sidewall source-side injection (SSI), and split-gate cells. This new method furnishes promising potentials: (i) it can eliminate the effect of process variations; (ii) the traditional source or drain capacitive coupling measurement becomes unnecessary; (iii) only a few dc measurements are needed; and (iv) even dummy transistors can be removed out. Therefore, the method is highly suitable as an in-line process monitor.
Forward bias enhanced channel hot electron injection for low-level programming improvement in multilevel flash memory
(2004-07-01)
Cho, CYS
;
Chen, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low-voltage programmed levels are hard to achieve in multilevel Flash memory using staircase CHEI (channel hot electron injection) programming. The reasons are that low-level programming marginally deviates from the linear relation between threshold voltage V-TH and control gate voltage V-CG. Forward bias enhancement of CHEI is proposed to overcome this drawback. It is demonstrated that the new technique creates a linear relation between V-TH and V-CG, validated down to a critical VCG that is at least I V lower than traditional CHEI. Through extensive measurements, it is further argued that the most suitable magnitude of forward bias is 0.5 V since (i) it produces the lowest program level of 1.4 V; and (ii) higher biases cause not only large current consumption but also worsened drain disturb performance in NOR array configuration. The corresponding linear relation with the unity slope is maintained after 1 05 program/erase cycling.
Improved subthreshold slope method for precise extraction of gate capacitive coupling coefficients in stacked gate and source-side injection flash memory cells
(2004-07-01)
Cho, CYS
;
Chen, MJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Existing subthreshold slope methods are shown to be far from accurate in extracting gate capacitive coupling coefficient alpha(G) in stacked gate flash memory cells. The origin of the error is systematically identified: (i) process variations induced mismatch and (ii) underlying bulk capacitive coupling. To alleviate such drawbacks, a new version of the subthreshold slope method at room temperature is established: alpha(G) = 0.06(n(f) - alpha(B))/s(f), where the subthreshold swing s(f) is from flash memory cells, the subthreshold slope factor nf is from dummy transistors via threshold voltage against source-to-substrate bias measurement, and the bulk coupling coefficient alpha(B) is from a linear extension of the dimensional dependencies in the literature. The resulting alpha(G) of around 0.55 again agrees consistently with those dependencies and once drain and source coupling experiment is performed, the relation of Sigma alpha(i) approximate to 1 is achieved for all involved coupling coefficients alpha(i)'s.. The sidewall source-side injection flash memory cells are also investigated. With the improved method, this manufacturing process is proved free of process variations issue and is characterized with alpha(G) of 0.374 and fringing capacitance of 0.204 fF. (C) 2004 Elsevier Ltd. All rights reserved.