Browsing by Author "Cho, Ming-Hsiang"

Now showing 1 - 5 of 5

A Flexible Microwave De-Embedding Method for On-Wafer Noise Parameter Characterization of MOSFETs
(2009-09-01)
Wang, Yueh-Hua
;
Cho, Ming-Hsiang
;
Wu, Lin-Kun
;
電信工程研究所
;
Institute of Communications Engineering
A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.
A novel electrically tunable RF inductor with ultra-low power consumption
(2008-04-01)
Cho, Ming-Hsiang
;
Wu, Lin-Kun
;
電信工程研究所
;
Institute of Communications Engineering
In this study, we propose for the first time an electrically and continuously tunable RF inductor using grounded metal oxide semiconductor (MOS) transistor as a control device. By adjusting the output resistance of the grounded MOSFET, the ground-return current can lead to a significant variation in series inductance. This proposed inductor structure was implemented in a standard CMOS process and characterized up to 30 GHz, which demonstrates maximum inductance variations of 32% and 58% at 5.8 and 18 GHz, respectively. The dc power consumption of the proposed design is kept within 50 mu W over the entire tuning range.
Miniature RF test structure for on-wafer device testing and in-line process monitoring
(2008-01-01)
Cho, Ming-Hsiang
;
Lee, Ryan
;
Peng, An-Sam
;
Chen, David
;
Yeh, Chune-Sin
In this brief, a miniature test structure for RF device characterization and process monitoring has been proposed. This new layout design can minimize the voltage drop across interconnects and can prevent capacitive coupling to devices. It consumes only 36% and 40% of the chip area of the conventional on-wafer and in-line test structures, respectively. The RF characteristics of the proposed test structure are shown to be in excellent agreement with those of the conventional ones.
Scalable short-open-interconnect S-Parameter de-embedding method for on-wafer microwave characterization of silicon MOSFETs
(2007-09-01)
Cho, Ming-Hsiang
;
Wang, Yueh-Hua
;
Wu, Lin-Kun
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.
Through-Silicon-Via Characterization and Modeling Using a Novel One-Port De-Embedding Technique
(2013-10-01)
Peng, An-Sam
;
Cho, Ming-Hsiang
;
Wang, Yueh-Hua
;
Wang, Meng-Fang
;
Chen, David
In this paper, a novel and simple one-port de-embedding technique has been applied to through-silicon-via (TSV) characterization and modeling. This method utilized pad, via, and line structures to extract the equivalent circuit model of TSV. The main advantage of this de-embedding method is that it can reduce the chip area to fabricate test element groups (TEGs) for measurements while keeping S-parameter measurement accuracies. We also analyzed the electrical characteristics of substrate coupling and TSV equivalent impedance. Our results shows good agreements between measurement data and the equivalent circuit model up to 20 GHz.