Browsing by Author "Cho, T. -C."

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A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing
(2014)
Lee, Y. -J.
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Cho, T. -C.
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Kao, K. -H.
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Sung, P. -J.
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Hsueh, F. -K.
For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (similar to 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. similar to 67mV/dec) and excellent on-off ratio (>10(6)) for both n and p channel devices. Threshold voltage (V-TH) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.
High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications
(2016-01-01)
Lee, Y. -J.
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Hong, T. -C.
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Hsueh, F. -K.
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Sung, P. J.
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Chen, C. -Y.
Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) ION and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high I-ON/I-OFF ratio and low subthreshold swing (S.S. similar to 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.
High Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technology
(2016)
Sung, P. -J.
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Cho, T. -C.
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Chen, P. -C.
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Hou, F. -J.
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Lai, C. -H
In this paper, strain effects on silicon n-channel gate-allaround (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (I-on/I-off > 10(9)) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.
Microwave Annealing
(2012)
Lee, Yao-Jen
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Cho, T. -C.
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Chuang, S. -S.
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Hsueh, F. -K.
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Lu, Y. -L.
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However the details of the kinetics and mechanisms for microwave annealing are far from well understood. Comparisons between MWA and RTA of dopants in implanted Si has been investigated to produce highly activated junctions. First, As, P-31, and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C.