Browsing by Author "Cho, Ta-Chun"

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Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal
(2014)
Wu, Chien-Ting
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Lee, Yao-Jen
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Hsueh, Fu-Kuo
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Sung, Po-Jung
;
Cho, Ta-Chun
A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
(2020-09-01)
Sung, Po-Jung
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Chang, Shu-Wei
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Kao, Kuo-Hsing
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Wu, Chien-Ting
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Su, Chun-Jung
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications
(2017-05-01)
Sung, Po-Jung
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Cho, Ta-Chun
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Hou, Fu-Ju
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Hsueh, Fu-Kuo
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Chung, Sheng-Ti
In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S. S.) of 65 mV/decade with ION/IOFF > 10(9); strained JL bulk FinFETs show an S. S. of 75 mV/decade with I-ON/I-OFF > 10(7). For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by ID-VG curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher ID and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.
Low-temperature Microwave Annealing Processes for Future IC Fabrication
(2014)
Lee, Yao-Len
;
Tsai, Bo-An
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Cho, Ta-Chun
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Hsueh, Fu-Kuo
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Sung, Po-Jung
Low temperature microwave annealing (MWA) for IC processing is promising. In this study, using microwave annealing for dopant activation and thermal stability of the high-k/metal gate is investigated. Implanted species, such as phosphorus, arsenic, and boron, can also be well-activated and diffusionless in Si after microwave annealing. The flat band voltage shift of metal gate was suppressed due to the low temperature process. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated by using low temperature MW A. In addition, the short channel effects in n & pMOSFETs annealed by MW A can be also improved due to the suppression of dopant diffusion and stabilization of EOT.
Low-Temperature Microwave Annealing Processes for Future IC Fabrication-A Review
(2014-03-01)
Lee, Yao-Jen
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Cho, Ta-Chun
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
;
Lu, Yu-Lun
Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C. Next, enhancing the substitutional carbon concentration ([C] sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.
Microwave Annealing of Phosphorus and Cluster Carbon Implanted (100) and (110) Si
(2013)
Cho, Ta-Chun
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Lu, Yu-Lun
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Yao, Jie-Yi
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Lee, Yao-Jen
;
Sekar, Karuppanan
Effects of low-temperature (approximate to 500 degrees C) microwave annealing (MWA) of Cluster-Carbon (C-7) and Phosphorus implants are compared with rapid thermal annealing (RTA) at 900 and 1000 degrees C for (100) and (110)-Si substrates. MWA annealing resulted in high levels of substitutional Carbon, 1.57% for (100) Si and 0.99% for (110) Si for C-7 implants. Addition of high-dose Phosphorus implants resulted in lower but still useful substitutional Carbon levels, 1.44% for (100) Si and 0.68% for (110) Si after MWA. RTA annealing at higher temperatures resulted in greatly reduced substitutional Carbon levels and deeper Phosphorus junctions. The effects of subsequent anneals by MWA and RTA methods are reported. MWA is shown to be a promising method for high-channel tensile strain in nMOSFETs with a substantially lower thermal budget than RTA. (C) 2013 The Electrochemical Society. All rights reserved.
Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices
(2017-01-01)
Chuang, Shang-Shiun
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
;
Chen, Henry J. H.
We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800 degrees C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of approximate to 15 nm, and peak concentration of approximate to 6 x 10(20) atoms/cm(3). The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA. (C) 2017 The Electrochemical Society. All rights reserved.