Browsing by Author "Cho, Wei-Han"

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A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection
(2017-04-01)
Du, Yuan
;
Cho, Wei-Han
;
Huang, Po-Tsang
;
Li, Yilei
;
Wong, Chien-Heng
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm(2) in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 mu W/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
A 16Gb/s 14.7mW Tri-Band Cognitive Serial Link Transmitter with Forwarded Clock to Enable PAM-16 / 256-QAM and Channel Response Detection in 28 nm CMOS
(2016)
Du, Yuan
;
Cho, Wei-Han
;
Li, Yilei
;
Wong, Chien-Heng
;
Du, Jieqiong
A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm(2) in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 mu W/Gb/s/dB considering channel condition.
A 38mW 40Gb/s 4-Lane Tri-Band PAM-4 / 16-QAM Transceiver in 28nm CMOS for High-Speed Memory Interface
(2016)
Cho, Wei-Han
;
Li, Yilei
;
Du, Yuan
;
Wong, Chien-Heng
;
Du, Jieqiong
A 7.5-mW 10-Gb/s 16-QAM Wireline Transceiver with Carrier Synchronization and Threshold Calibration for Mobile Inter-chip Communications in 16-nm FinFET
(2019-01-01)
Du, Jieqiong
;
Wong, Chien-Heng
;
Tu, Yo-Hao
;
Cho, Wei-Han
;
Li, Yilei
A compact energy-efficient 16-QAM wireline transceiver with carrier synchronization and threshold calibration is proposed to leverage high-density fine-pitch interconnects. Utilizing frequency-division multiplexing, the transceiver transfers four-bit data through one RF band to reduce inter-symbol interferences. A forwarded clock is also transmitted through the same interconnect with the data simultaneously to enable low-power PVT-insensitive symbol clock recovery. A carrier synchronization algorithm is proposed to overcome nontrivial current and phase mismatches by including DC offset calibration and dedicated I/Q phase adjustments. Along with this carrier synchronization, a threshold calibration process is used for the transceiver to tolerate channel and circuit variations. The transceiver implemented in 16-nm FinFET occupies only 0.006-mm(2) and achieves 10 Gb/s with 0.75-pJ/bit efficiency and <2.5-ns latency.
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2019-06-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Cho, Wei-Han
;
Huang, Rulin
This paper presents a millimeter-wave (127 GHz) CMOS transceiver with a digital pre-distortion capable PAM-4 modulator for contactless communications. The transmitter upconverts PAM-4 modulated baseband signals through a free-running 127-GHz oscillator and single-balanced mixer, and it delivers PAM-4 modulated carrier signals to a folded-dipole antenna, which is designed on a FR408HR substrate. The receiver's low-noise amplifier provides a 10-dB gain, and the self-mixer downconverts carrier-modulated PAM-4 signals to base-band signals without the necessity of carrier synchronization. The PAM-4 modulator pre-distorts the baseband signals and corrects the non-linear characteristics of the transmitter's upconversion mixer and the receiver's downconversion self-mixer. Designed and fabricated in a 65-nm CMOS process, the demonstrated system transfers 20 Gb/s of PAM-4 modulated data through a 1-mm air gap and consumes 79.5 mW (transmitter: 50.8 mW and receiver: 28.7 mW) of power under a 1.2-V supply, achieving a 3.98-pJ/bit energy efficiency. The communication distance is extended to 3 cm by inserting a dielectric waveguide between the same transceiver.
Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI)
(2017-12-01)
Kim, Yanghyo
;
Cho, Wei-Han
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Du, Yuan
;
Cong, Jason
;
Itoh, Tatsuo