Browsing by Author "Chou, CY"

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A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications
(2003)
Wu, CY
;
Chou, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
(2004-03-01)
Wu, CY
;
Chou, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.
The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications
(2002)
Chou, CY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a new technique to implement an active polyphase filter. In this design, the currents mirrored from capacitors and transistors realize the high-pass and low-pass signals, respectively The multi-stage structure, which is commonly used in RC networks, expands the frequency bandwidth. Furthermore, a constant-gin bias circuit is used to decrease the sensitivities of gain and bandwidth to temperature and process variations. HSPICE is simulated to confirm the performances. The voltage gain is 8.1dB and THD is -48dB when a +20MHz, 100mV quadrature signal is applied. The image-rejection ratio exceeds 60dB over the frequency range of -15.4MHz similar to - 44.6MHz. The polyphase filter is implemented with 0.18mum CMOS technology and the power dissipation is 6.85mW with a 1.8V power supply. Simulations of various corners and temperatures show that the variations in gain and frequency are effectively controlled.
The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers
(2005-05-01)
Chou, CY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, a new technique to implement the transfer function of polyphase filter with CMOS active components is proposed and analyzed. In the proposed polyphase filter structure, the currents mirrored from capacitors and the transistors in a single-stage are used to realize high-pass and low-pass functions, respectively. The multistage structure expands the frequency bandwidth to more than 20 MHz. Furthermore, a constant-gm bias circuit is employed to decrease the sensitivity of image rejection to temperature and process variations. HSPICE simulations are performed to confirm the performance. With the current-mode operation, the low-voltage version of proposed active polyphase filters was designed. It can be operated at IN power supply with similar performance but with only 50% of the power dissipation of the normal-voltage version. The proposed four-stage polyphase filter is fabricated in 0.25-μ m CMOS 1P5M technology. The measured image rejection ratio is higher than -48 dB at frequencies of 6.1 MHz &SIM; 30 MHz. The measured voltage gain is 6.6 dB at 20 MHz and IIP3 is 8 dBm. The power dissipation is 11 mW at a supplied voltage of 2.5 V and the active chip area is 1162 x 813 μ m(2).