Browsing by Author "Chou, Chen-Han"

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3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor
(2016)
Chou, Chen-Han
;
Hsu, Chung-Chun
;
Yeh, Wen-Kuan
;
Chung, Steve S.
;
Chien, Chao-Hsin
We propose a new device structure, namely CAA T-FinFET, for 10nm MOSFETs with using contact all around (CAA) structure. According to 3D simulation study, the CAA T-FinFET possess many advantages over the conventional FinFET structure, such as short channel effect (SCE) suppression by self-aligned oxide (SA oxide), parasitic leakage path isolation with body-tied bulk, sourceldrain series resistance reducing and fin to fin pitch scaling by contact all around process. Base on heterogeneous bulk for strain application, CAA T-FinFET has better electrical performance and easy process control. All these advantages are achieved by depositing a self-aligned oxide after isotropic etching in SID region. Contact all around can efficiently solve the series resistance degradation and pitch scaling by replacing diamond-shape SID stressor with the full contact metal. CAA T-FinFET has high potential to be applied to the varied heterogeneous substrate and high mobility channel (Ge and III-V) MOSFETs by SA oxide.
3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect Transistor
(2015)
Chou, Chen-Han
;
Hsu, Chung-Chun
;
Chung, Steve S.
;
Chien, Chao-Hsin
;
電子工程學系及電子研究所
We propose a novel device structure, namely T-FinFET, for sub-14nm MOSFET with using lighter anti punch through (APT) implant. According to 3D TCAD simulation, the T-FinFET is found to posses many advantages over the normal FinFET, such as better short channel effect (SCE) and drain induced barrier lowering (DIBL), having smaller S/D capacitance and junction leakage and fewer masks. Compared to gate-all-around (GAA) structure, the T-FinFET also has compatible electrical performance. All these features are obtained by depositing a self-aligned (SA) oxide after recessing the Si fin in the S/D region. It can be applied to Ge and III-V MOSFETs for suppressing the SCEs and S/D leakage, arising from higher permittivity and lower band gap than Si.
Comparison of the Physical and Electrical Properties of HfO2/Al2O3/HfO2/GeOx/Ge and HfO2/Al2O3/GeOx/Ge Gate Stacks
(2019-08-01)
Tsai, Yi-He
;
Chou, Chen-Han
;
Li, Hui-Hsuan
;
Yeh, Wen-Kuan
;
Lino, Yu-Hsien
A high-quality HfGeOx interfacial layer (IL) was formed in a HfO2/Al2O3/HfO2/GeOx gate stack through thermal annealing. The diffusing of GeO into the HfO2 layer led to the mixing of the GeOx and HfO2 layers, as identified through energy-dispersive X-ray Spectroscopy (EDX). X-ray photo-electron spectroscopy (XPS) data for HfGeOx IL confirmed the formation of Ge-O-Hf bonds owing to the induced shift of the Ge3d(ox) spectra to lower binding energies. The electrical and reliability data indicated that the capacitor with HfGeOx IL presented not only lower interface states density (Dit, approximately 7 x 10(11) eV(-1)cm(-2)) but also less Dit increment (approximately 3 x 10(11) eV(-1)cm(-2)) after stressing than did the capacitor without the HfGeOx IL. Moreover, the Ge p-metal-oxide-semiconductor field-effect transistor HfGeOx IL exhibited a high effective hole mobility (approximately 704 cm(2)/V . s).
Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer
(2019-02-01)
Tsai, Yi-He
;
Chou, Chen-Han
;
Chung, Yun-Yan
;
Yeh, Wen-Kuan
;
Lin, Yu-Hsien
HfO2-based gate stacks with titanium (Ti) incorporated into a GeOx interfacial layer (IL) were fabricated on p-Ge substrates. X-ray photoelectron spectroscopy results, incorporating Ti, can efficiently suppress the GeO volatilization. This contributed to achievement of an equivalent oxide thickness of approximately 0.8 nm, a low interface states density D-it of approximately 2.5 x 10(11) eV(-1)cm(-2), and a smaller D-it increment of approximately 1 x 10(11) eV(-1)cm(-2) after constant negative voltage stress at a field of 8 MV/cm. Therefore, Ti is appropriate for improving the quality of GeOx through high temperature annealing.
Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs
(2016-07)
Hsu, Chung-Chun
;
Chi, Wei-Chun
;
Tsai, Yi-He
;
Chou, Chen-Han
;
Chen, Che-Wei
This paper presents a high-performance Ge p-channel MOSFET (pMOSFET) with NiGePt as a ternary-phase alloy of Schottky source/drain (S/D) formed through low-temperature microwave-activated annealing (MWA). We fabricated a NiGePt alloy contact with uniform crystallinity through structural engineering and MWA. We clarified the phenomena of thermal reaction and diffusion for forming ternary-phase alloys using MWA properties such as thermal dynamics and ionic transportation. The ternary-phase NiGePt alloy is crucial for improving the off-leakage current of the junction. A lower process temperature is beneficial for eliminating surface roughness and reducing alloy agglomeration of the Schottky contact S/D. Consequently, the fabricated NiGePt/n-Ge Schottky junction exhibited a high effective barrier height (Phi(Bn)) of 0.59 eV, resulting in a high junction current ratio of more than 10(5) at an applied voltage of vertical bar V-a vertical bar = 1 V. In addition, we exploited the advantages of low-temperature microwave annealing to fabricate the pMOSFET, which includes a GeO2 passivation layer and a Schottky S/D. Our ternary Schottky Ge pMOSFET (L = 4 mu m) exhibited high I-ON/I-OFF ratios of approximately 3.7x10(3)(I-D) and 1.3x10(5)(I-S) and a moderate subthreshold swing of 126 mV/dec.
Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping
(2017-05-01)
Chou, Chen-Han
;
Tsai, Yi-He
;
Hsu, Chung-Chun
;
Jau, Yu-Hau
;
Lin, Yu-Hsien
In this paper, we demonstrated the enhancement of thermal stability of nickel germanide (NiGe) alloy up to 600 degrees C by using titanium nitride (TiN) metal capping. A high ION/IOFF ratio of 2.9 x 105 was achieved by capping TiN metal on Ni for NiGe alloy formation at 600 degrees C. Detailed analyses were performed for realizing the mechanism for TiN capping on NiGe/Ge, including vertical element diffusion profile observation through depth-profiling X-ray photoelectron spectroscopy (XPS), element diffusion distribution by energy-dispersive X-ray spectroscopy mapping, and direct junction leakage current path detection by conductive atomic force microscopy. The experimental results indicated that TiN capping can reduce the risk of agglomeration and form a graded NiGe/Ge Schottky junction that is beneficial for suppressing the degradation of junction leakage. Subsequently, we compared the electrical performance of TiN/NiGe/n-Ge at various N/Ti ratios of TiNs. Based on the depth-profiling XPS results and electrical performance, TiN with an N/Ti ratio of approximately 1: 1 can resist the Ni and Ge diffusion, which facilitates the suppression of the agglomeration process. However, the TiN capping layers with an N/Ti ratio of less than approximately 1:1 (Ti-rich) were not favorable for resisting Ni and Ge diffusion.
First Experimental Demonstration and Mechanism of Abnormal Palladium Diffusion Induced by Excess Interstitial Ge
(2018-11-01)
Chou, Chen-Han
;
Shih, An-Shih
;
Yu, Shao-Cheng
;
Lin, Yu-Hsi
;
Tsai, Yi-He
This letter represents the first direct experimental demonstrations and mechanism proposal regarding abnormal palladium diffusion into germanium (Ge). Our experiments indicated that excess Ge atoms among palladium germanide alloy formation indirectly induce the abnormal out-diffusion of mass palladium atoms into Ge. Consequently, palladium germanide alloy on both n-type and p-type Ge form ohmic-like Schottky junctions. To identify this phenomenon, first-principle calculations and technology computer-aided design simulation were used to evaluate the electrical influence of palladium atoms in Ge. We discovered that the activated palladium atoms in Ge induce large midgap bulk-trap states, which contribute to a severe increment of trap-assisted tunneling current at the palladium germanide/Ge junction.
High Performance Ge Schottky PMOSFETs with Ternary-Phase Alloy
(2016-01-01)
Hsu, Chung-Chun
;
Chi, Wei-Chun
;
Chou, Chen-Han
;
Chen, Che-Wei
;
Chien, Hung-Pin
This work demonstrates high-performance Ge p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) [1] with ternary-phase NiGePt alloy Schottky source/drain (S/D) by low-temperature microwave-activated annealing (MWA) [2]. Process flow of Shcottky junctions is shown in Fig. 1. Interestingly, the formed NiGePt alloy is nearly single crystalline. We found the formation of ternary-phase alloy NiGePt seems very helpful in suppressing the off-leakage of junction, as shown in Fig. 2. The fabricated NiGePt/N-Ge Schottky junction depicted an impressive effective barrier height (Phi(Bn)) of similar to 0.59 eV for electrons, leading to a high junction current ratio of >10(5) at the applied voltage of vertical bar V-a vertical bar = 1 V. Slight increase with increasing deposited Pt thickness can be explained by the improved series resistance, as shown in Fig. 2. The lower process temperature of MWA as compared to the conventional thermal annealing is beneficial for eliminating surface roughness, reducing alloy agglomeration of Schottky contact S/D. As a consequence, we employed the advantages of low-temperature MWA to fabricate the Schottky S/D PMOSFETs. With forming gas annealing, the Ge PMOSFET (L = 4 mu m) showed a very high output current of 33.5 mu A/mu m at V-GS-V-T = -2.4 and V-DS = -2 V. Our ternary Schottky PMOSFET exhibited a high I-ON/I-OFF ratios of similar to 3.7 X 10(3)(I-D) and similar to 1.3 X 10(5)(I-S), and a moderate subthreshold swing of 126 mV/dec, as shown in Figs. 3.
Improving Thermal Stability and Interface State Density of High-kappa Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium
(2016-11)
Tsai, Yi-He
;
Chou, Chen-Han
;
Shih, An-Shih
;
Jau, Yu-Hau
;
Yeh, Wen-Kuan
We propose a new HfGeOx interfacial layer (IL) for the high-kappa gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeOx IL. We inserted an additional HfO2 layer after the formation of GeOx in the HfO2/Al2O3/GeOx/Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 degrees C. We speculate that the improvement originates from the formation of HfGeOx through the combination of HfO2 and GeOx, according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high-kappa gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density (D-it) of approximately 3.3 x 10(11) eV(-1) cm(-2), and an impressive gate leakage current of approximately 2.2 x 10(-6) A/cm(2) at VFB-1V.
Incorporating Yttrium into a GeO Interfacial Layer with HfO2-Based Gate Stack on Ge
(2018-01-01)
Chou, Chen-Han
;
Lu, Yu-Hong
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Tsai, Yi-He
;
Shih, An-Shih
;
Yeh, Wen-Kuan
In this study, we employed the electrical and material properties of various interfacial layers (ILs) such as GeO and YGeO on a Ge substrate. First, capacitors using various ILs with HfO2-based gate stacks were developed. The capacitor using YGeO IL exhibited a low interface state density (D-it) of 2.5 x 10(11) eV(-1)cm(-2) and an equivalent oxide thickness of 1.8 nm. Next, a reliability test for constant voltage stress was conducted for further studying the YGeO ILs. The capacitors with YGeO ILs presented higher immunity for Dit degradation. Further, to understand the material properties of various ILs, a simple experiment on capping a Si chip on GeO or YGeO/Ge samples through high-temperature annealing was conducted. We observed that Ge and GeO vapors can be absorbed by Si and detected through X-ray photoelectron spectroscopy (XPS). XPS spectra of Si chips capped on GeO IL presented obvious features of Ge and GeO through annealing at 500 degrees C; however, the XPS spectra of Si chips capped on YGeO IL presented no features, indicating that YGeO ILs had higher thermal stability than GeO ILs. To further analyze the HfO2-based gate stacks with various ILs, Ge diffusion into a high-k HfO2 layer was investigated through angle-resolved XPS. We observed that YGeO ILs with HfO2-based gate stacks can reduce Ge diffusion into a HfO2 layer. (C) 2018 The Electrochemical Society.
Integration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantation
(2016)
Chou, Yu-Che
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Hsu, Chung-Chun
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Chun, Cheng-Ting
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Chou, Chen-Han
;
Tsai, Ming-Li
In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I-ON/I-OFF ratio and lower junction leakage (4x10(-3)mu A/cm(2)). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6x10(-6)mu A/cm(2))as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I-ON/I-OFF ratio similar to 8x10(3) (I-S) than the conventional Ge FinFET (I-ON/I-OFF similar to 2x10 (3)).
Integration of microwave-annealed oxidation on germanium metal-oxide-semiconductor devices
(2018-09-01)
Hsu, Chung-Chun
;
Chi, Wei-Chun
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Tsai, Yi-He
;
Tsai, Ming-Li
;
Wang, Shin-Yuan
In this paper, a method that entails using microwave thermal oxidation to form a high-quality gate dielectric on Ge through surface passivation at considerably low temperatures (<400 degrees C) is presented. Formation of the GeOx layer was confirmed by x-ray photoelectron spectroscopy. To reduce the bulk trap density and interface trap density (D-it), microwave thermal oxidation was employed for post-deposition microwave thermal oxidation after the deposition of Al2O3 through atomic layer deposition. Tiny frequency dispersion in capacitance measurement and a low D-it value of 5.9 x 10(11) cm(-2) eV(-1) near the midgap confirmed a desirable passivation effect, which was favorable in mitigating the formation of dangling bonds on the Ge surface. A small hysteresis in capacitance was also observed, suggesting that the bulk dielectric was of high quality. On the basis of these characteristics, microwave-activated GeOx is a promising passivation layer material for aggressively scaled Ge-related metal oxide semiconductor devices. Published by the AVS.
Low-Leakage Tetragonal ZrO2 (EOT < 1 nm) With In Situ Plasma Interfacial Passivation on Germanium
(2016-02)
Chou, Chen-Han
;
Chang, Hao-Hsuan
;
Hsu, Chung-Chun
;
Yeh, Wen-Kuan
;
Chien, Chao-Hsin
We successfully fabricated gate stacks (ZrO2/GeOx/Ge) with a subnanometer equivalent oxide thickness (EOT) and low-leakage current on n-/p-Ge through plasma-enhanced atomic layer deposition (ALD). A 0.78-nm-thick GeOx was formed through plasma oxidation (i.e., in situ plasma interfacial passivation, followed by 3.48-nm-thick ZrO2 growth in the same ALD reactor). A subnanometer EOT of similar to 0.9 nm was achieved with a relatively high dielectric constant (roughly 30) of tetragonal-phase ZrO2. The gate leakage was similar to 1 x 10(-4) A/cm(2) at V-FB - 1 V, and roughly 5 x 10(-5) A/cm(2) at V-FB + 1 V on p-and n-type Ge, respectively. Our ZrO2 stabilized in the tetragonal phase, when the post-deposition annealing temperature, was higher than 500 degrees C. Therefore, the proposed scheme is simple and effective for use in pursuing an ultralow EOT gate dielectric on Ge.
Phase-separation phenomenon of NiGePt alloy on n-Ge by microwave annealing
(2018-04-30)
Hsu, Chung-Chun
;
Lin, Kun-Lin
;
Chi, Wei-Chun
;
Chou, Chen-Han
;
Luo, Guang-Li
During the formation of distinct bilayer NiGePt alloy, a phase-separation phenomenon was observed using microwave annealing and structural engineering. The microstructures of bilayer NiGePt [PtGe(Ni)-NiGe(Pt)] alloys fabricated with 10-nm Ni and various thicknesses of Pt (5, 10, and 15 nm) were characterized. Within the same thermal budget as microwave annealing, the diffusion of Ni exhibited stronger alloy formation ability with Ge and drilled through the Pt layer without resistance. The higher diffusivity of Ni atoms dominated the diffusion of Ni through the Pt layer to form a stable crystalline layer, NiGe(Pt). Ge diffused outwardly toward the Pt layer to form a PtGe(Ni) layer. This special phenomenon of bilayer alloy formation was elucidated using nanobeam electron diffraction by transmission electron microscopy in conjunction with energy-dispersive spectrometry. Comparing the differences in metal alloys between microwave and rapid thermal annealing, microwave annealing formed a bilayer alloy more apparently than rapid thermal annealing. The results and electrical characteristics indicated that a thicker Pt layer for forming a bilayer NiGePt alloy with alloy separation could also effectively improve the leakage current of NiGePt [PtGe(Ni)- NiGe(Pt)]/n-Ge Schottky junctions. (c) 2018 Elsevier B.V. All rights reserved.