Browsing by Author "Chou, Fang-Ting"

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A compact 12-bit DAC with novel bias scheme
(2014-01-01)
Chou, Fang-Ting
;
Hung, Chung-Chih
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
A compact and low-power design of a 12-bit binary-weighted current-steering DAC is presented. Instead of 4096 unit current cells, the proposed design uses 192 unit current sources with two reference currents. The silicon area of the generation circuit of two reference currents is very compact as well. The area of the total current source arrays is smaller than four times the area of 6-bit current source arrays, which has significantly reduced the dimension of the analog part of a conventional 12-bit DAC. The proposed DAC achieves 400 MS/s update rate and consumes 38.7 mW from single 1.8 V supply.
A low-glitch binary-weighted DAC with delay compensation scheme
(2014-05-01)
Chou, Fang-Ting
;
Chen, Chia-Min
;
Hung, Chung-Chih
;
資訊工程學系
;
Department of Computer Science
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Omega termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 mu m CMOS technology and dissipates 19 mW from a single 1.8 V power supply.
A Novel 12-bit Current-Steering DAC with Two Reference Currents
(2015)
Chou, Fang-Ting
;
Chen, Zong-Yi
;
Chu, Hsing-Chien
;
Hung, Chung-Chih
;
電機學院
This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design is compact and consumes low static power. The active area of the 12-bit DAC is 0.36mm(2) approximately. This chip was fabricated by a standard 0.18 mu m CMOS technology, and consumes 38mW at 180MS/s update rate with 1.8V supply voltage.
A Novel Glitch Reduction Circuitry for Binary-Weighted DAC
(2014-01-01)
Chou, Fang-Ting
;
Chen, Chia-Min
;
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機資訊學士班
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm(2) core area, and dissipates 19mW from a single 1.8V power supply.
Dual-Output Switched-Capacitor DC-DC Converter With Peseudo-Three-Phase Swap-and-Cross Control and Amplitude Modulation Mechanism
(2013)
Chen, Chia-Min
;
Chiang, Chun-Yen
;
Du, Chen-Cheng
;
Chou, Fang-Ting
;
Hung, Chung-Chih
This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The two outputs were regulated at 2.5 V and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz. The maximal peak-to-peak output ripple voltages for the two outputs under 100 mA load currents were suppressed to below 26 mV and 20 mV, respectively.
Dual-output switched-capacitor DC-DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism
(2018-06-01)
Chen, Chia-Min
;
Su, Chung-Cheng
;
Chou, Fang-Ting
;
Hung, Chung-Chih
;
電機工程學系
This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC-DC converter was implemented in a standard 0.18-mu m 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.
Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
(2016-06)
Chou, Fang-Ting
;
Hung, Chung-Chih
;
電機學院
;
College of Electrical and Computer Engineering
This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary-weighted current switches in a current-steering digital-to-analog converter (DAC). The method was proved successfully by a 10-bit 400-MHz pure binary-weighted current-steering DAC with a minimum number of retiming latches. The experiment results yield very low-glitch energy during major carry transitions at output, which is <1 pVs. This brief utilizes a layout structure to improve the spurious-free dynamic range at high signal frequencies. This chip was implemented in a standard 0.18-mu m CMOS technology and consumes 20.7 mW at 400 MS/s.