Browsing by Author "Chou, Hung-Mu"

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A compact model for electrostatic discharge protection nanoelectronics simulation
(2005)
Chou, Hung-Mu
;
Yu, Shao-Ming
;
Lee, Jam-Wem
;
Li, Yiming
;
電信工程研究所
In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.
A floating gate design for electrostatic discharge protection circuits
(2007-02-01)
Chou, Hung-Mu
;
Lee, Jam-Wen
;
Li, Yiming
;
電信工程研究所
;
友訊交大聯合研發中心
In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved by adding a switch device and a negatively biased circuit at the gate of ESD protection devices. Robustness and leakage of ESD protection circuit are improved. The circuit suits thin thickness of gate oxide of complementary metal oxide semiconductor (CMOS) devices due to an elimination of oxide damage. This approach benefits design of very large-scaled integration circuit and implementation of system-on-chip with sub-100 nm CMOS devices. (c) 2006 Elsevier B.V. All rights reserved.
Hybrid evolutionary approach to optimal design of CMOS LNA integrated circuits
(2005)
Li, Yiming
;
Chou, Hung-Mu
;
電信工程研究所
;
Institute of Communications Engineering
In this work we propose a hybrid intelligent circuit optimization technique for low noise amplifier (LNA) circuit. This method combines with the genetic algorithm (GA), Levenberg-Maxquardt (LM) method, and circuit simulator to perform automatic LNA circuit optimization. For a given LNA circuit, the optimization method considers the electrical specification such as S parameters: S-11, S-12, S-21, S-22, K factor, the noise figure, and the input third-order intercept point, simultaneously. The optimization procedure starts with loading the necessary parameters for circuit simulation, and then calls the circuit simulator for circuit simulation and evaluation. Sixteen optimized parameters of the LNA circuit composed with 0.18 mu m metal-oxide-silicon filed effect transistors (MOS-FETs) are acquired by our developed optimization prototype, where the aforementioned seven specifications axe all matched. The proposed circuit optimization method shows its robustness and practicability on radio-frequency (RF) circuit and wireless system on chip (SoC) design.
Parallel simulation of deep sub-micron double-gate metal-oxide-semiconductor field effect transistors
(2005)
Yu, Shao-Ming
;
Chou, Hung-Mu
;
Lo, Shih-Ching
;
資訊工程學系
;
Department of Computer Science
Drift-Diffusion Density Gradient model (DD-DG) is the most popular model for simulating carrier transport phenomena in sub-micron semiconductor device, especially in two- or three-dimensional space. In deep sub-micron regime, the width effects cannot be neglected while simulating, i.e., three-dimensional simulation must be considered. However, three-dimensional computing is time-consuming. Fortunately, the dilemma of time consuming or rough approximation can be overcame by advanced computing technique. In this paper, we employ a parallel direct solving method to simulate double-gate metal-oxide-semiconductor field effect transistors (DG-MOSFET). The computational benchmarks of the parallel simulation, parallel speedup, load balance, and efficiency are studied in this work. Parallel numerical simulation of semiconductor devices is shown to be an indispensable tool for fast characterization and optimal design of semiconductor devices.
Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors
(2004-10-01)
Li, Yiming
;
Lee, Jam-Wem
;
Chou, Hung-Mu
;
電子物理學系
;
友訊交大聯合研發中心
In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (RSiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (similar to 8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V-t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C-G) are estimated with respect to different gate length (L-G), gate bias (V-G), and R-SiGe. For short channel effects, such as V-t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.