Browsing by Author "Chou, JW"

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An anomalous crossover in Vth roll-off for indium-doped nMOSFETs
(2000-09-01)
Chang, SJ
;
Chang, CY
;
Chen, CM
;
Chou, JW
;
Chao, TS
The effects of indium channel implant energy on short-channel effect (SCE) and narrow channel effect (NCE) were studied on NMOS devices down to 0.1 mu m channel length. An anomalous crossover in Vth roll-off curves was observed, for the first time, on indium-implanted splits with different implant energies. This intriguing finding, together with the observed reduction in reverse narrow channel effect (RNCE) and effective channel length with reducing indium implant energy, can be consistently explained by the suppression of transient enhanced diffusion (TED) of channel impurity due to indium deactivation.
Optimization of short channel effect by arsenic P-Halo implant through polysilicon gate for 0.12uw P-MOSFET
(2000)
Chen, C
;
Chang, CY
;
Chou, JW
;
Huang, CT
;
Lin, KC
Excellent PMOS short channel effect is achieved by using high energy, large tilt angle arsenic implant as P-Halo. For the first time, it was found that the tail profile of P-Halo implant through the polysilicon gate, therefore, the channel concentration is modulated not only laterally from gate edge but also vertically from top of the polysilicon gate and it resulted in very flat short channel behavior. The effect of arsenic P-Halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate oxide integrity was examined by Q(BD) and it passed the lifetime of 10 years at different conditions of P-Halo implants. Excellent performance of 0.12um PMOSFET is also demonstrated in this work.
Optimization of short channel effect with arsenic halo implant through polysilicon gate
(2001-09-01)
Chen, CM
;
Chang, CY
;
Chou, JW
;
Cheng, YC
;
電子工程學系及電子研究所
Excellent p-type metal oxide semiconductor (PMOS) short channel effect is achieved by using a high-energy, large tilt angle arsenic implant as a P-channel halo. For the first time, it was found that the dopant profile of Halo was implanted through the poly-silicon gate. The channel concentration is modulated not only laterally from the gate edge but also vertically from the top of the polysilicon gate and this resulted in very flat short channel behavior. The effect of the arsenic halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate-oxide integrity was examined by charge to break down (Q(BD)). Excellent performance of 0.12 mum PMOSFET is also demonstrated in this work.
Shallow-trench isolation with raised-field-oxide structure
(2000-03-01)
Chen, CM
;
Chang, CY
;
Chou, JW
;
Lur, W
;
Sun, SW
This paper describes a novel shallow-trench isolation (STI) structure to suppress the corner metal-oxide semiconductor field-effect transistor (MOSFET) inherent to trench isolation. A gate oxide and a thin polysilicon layer are first processed, and are then followed by the STI process. With this raised-field-oxide structure, the anomalous subthreshold conduction of the shallow-trench isolated MOSFETs due to electric-field crowding at the active edge has been successfully eliminated. No inverse-narrow-width effect is observed as the device width has been scaled down to 0.3 mu m. The raised-field-oxide structure provides a larger process margin for planarization, and good device characteristics were achieved by this novel STI structure.
The effects of super-steep-retrograde indium channel profile on deep submicron n-channel metal-oxide-semiconductor field-effect transistor
(2001-01-01)
Chen, CM
;
Chang, SJ
;
Chou, JW
;
Lin, T
;
Yeh, WK
A complete study on the effects of indium channel implant energy on transistor characteristics including carrier mobility, drain current, drain induce barrier lowering (DIBL), device breakdown, junction leakage, impact ionization rate and hot-carrier degradation were performed on 0.1 mum devices. It was found that devices with super-steep-retrograde (SSR) indium channel profile depict higher transconductance in linear region, albeit the saturation drive current is lower, compared to the conventional BF2-doped control. In addition, In-doped devices also depict improved DIBL, I-on-I-off current ratio and transistor breakdown voltage. Finally, by increasing the indium implant energy, devices depict an improved transconductance, reduced DIBL and hot-carrier degradation, while suffering larger junction leakage and capacitance.