Browsing by Author "Chou, KY"

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Active circuit's under wire bonding I/O, pads in 0.13 mu m eight-level Cu metal, FSG low-K inter-metal dielectric CMOS technology(+)
(2001-10-01)
Chou, KY
;
Chen, MJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active circuits in terms of ring oscillator are moved to the place under the wire bonding pads in 0.13 mum fall eight-level copper metal complementary metal-oxide-semiconductor process with fluorinated silicate glass low-k inter-metal dielectric. The bond pad with the 12 K Angstrom thick aluminum metal film. as a bonding mechanical stress buffer layer is deposited on the topmost copper metal layer. No noticeable degradations in gate delay or cycle time of ring oscillator are detected in a variety of test structures subjected to bonding mechanical stress and thermal cycling stress. This indicates that the underlying process technology may be reliable and manufacturable in placing active circuits under the bonding pads and thereby the die area utility is recovered fully. More evidence is created from transmission fine pulsing experiments as well as capacitive-coupling experiments.
Active devices under CMOS I/O pads
(2002-12-01)
Chou, KY
;
Chen, MJ
;
Liu, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductoir process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V-t2, I-t2) of ESD protection devices under various metal level stack structures, shows that i) I-t2 depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V-t2 increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and dc electrical stress by transmission line pulse, as well as ac electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads is independent of bonding pad metal level structures.
ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology
(2001-07-01)
Chou, KY
;
Chen, MJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 mum full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD). The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V-t2, I-t2). High current I-V measured from the different level metal layers stack structures shows that 1) I-t2 depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V-t2 increases with the number of metal layers. The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device. Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications.