Browsing by Author "Chou, Teyuh"

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3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
(2016-09-09)
Wang, I-Ting
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Chang, Chih-Cheng
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Chiu, Li-Wen
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Chou, Teyuh
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Hou, Tuo-Hung
The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaOx/TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
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Liu, Jen-Chieh
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Shen, Yu-Lin
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Chou, Teyuh
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Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Development of Three-Dimensional Synaptic Device and Neuromorphic Computing Hardware
(2016-01-01)
Wang, I-Ting
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Chou, Teyuh
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Chiu, Li-Wen
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Chang, Chih-Cheng
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Hou, Tuo-Hung
To facilitate the development of low-cost, low-power, and high-density hardware neural networks, we have successfully developed a Ta/TaOx/TiO2/Ti RRAM-based synaptic device. The device exhibits numerous synaptic functions resembling those in biological synapses, including synaptic plasticity of potentiation and depression, spike-timing dependent plasticity, paired-pulse facilitation and a transition from short-term to long-term memory. We further demonstrate 3D high-density, high-connectivity integration of the Ta/TaOx/TiO2/Ti device, and the device exhibits excellent uniformity among interlayer and intralayer cells in a 4 x 4 3D two-layer cross-point array. Finally, we investigate the influence of nonlinearity of synaptic weight updates on neuromorphic computing. A state-independent training scheme is proposed to improve linearity and fault tolerance of training accuracy.
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
(2018-03-01)
Chang, Chih-Cheng
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Chen, Pin-Chun
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Chou, Teyuh
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Wang, I-Ting
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Hudec, Boris
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.