Browsing by Author "Chou, Tung-Huan"

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3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
;
Shieh, Jia-Min
;
Huang, Wen-Hsien
;
Hsieh, Wei-Shang
;
Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
Impact of channel dangling bonds on reliability characteristics of flash memory on poly-Si thin films
(2007-04-01)
Lin, Yu-Hsien
;
Chien, Chao-Hsin
;
Chou, Tung-Huan
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this letter, we fabricated the poly-Si-oxide-nitride-oxide-silicon (SONOS)-type Flash memories on polycrystalline-silicon thin films and found that dangling bonds presented along the grain boundaries in the channel significantly influence their reliability characteristics in the aspects of charge storage, drain disturbance, and gate disturbance. Employing a powerful defect passivation technique, i.e., NH3 plasma treatment, the charge storage capability was clearly observed to be remarkably improved. Even so, the hydrogenated polycrystalline-silicon thin-film transistors (poly-Si-TFTs) still suffered from serious drain and gate disturbances, which exhibited behaviors that are quite specific and undoubtedly distinct from those observed in the conventional SONOS-type memories on single crystalline substrates.
Low-temperature polycrystalline silicon thin-film flash memory with hafnium silicate
(2007-03-01)
Lin, Yu-Hsien
;
Chien, Chao-Hsin
;
Chou, Tung-Huan
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (<= 600 degrees C). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (> 10(6) s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory.