Browsing by Author "Chou, Yu-Che"

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Impact of the Crystal Phase of ZrO2 on Charge Trapping Memtransistor as Synaptic Device for Neural Network Application
(2020-01-01)
Chou, Yu-Che
;
Tsai, Chien-Wei
;
Yi, Chin-Ya
;
Chung, Wan-Hsuan
;
Chien, Chao-Hsin
In this work, we investigated the effects of the crystal phase of ZrO2 on charge trapping memtransistors (CTMTs) as synaptic devices for neural network applications. The ZrO2 deposited through thermal (t-ZrO2) atomic layer deposition (ALD) and plasma (p-ZrO2) ALD were analyzed using an X-ray diffractometer, which indicated that the t-ZrO2 consisted of pure cubic phase, whereas p-Zr-O2 consisted of both cubic and tetragonal phases. Through X-ray photoelectron spectroscopy analysis, we then constructed the energy band diagram of the gate stacks. The Delta E-C of t- and p-ZrO2 with respect to tunneling and blocking Al2O3 were 1.84 and 1.19 eV respectively. Because of the relatively large Delta E-C of t-ZrO2, the window of the flat band voltage (V-FB) shift extracted from charge trapping capacitors was enlarged by 591.9 mV more than the one using p-ZrO2 as the charge trapping layer. Retention was also improved by 10.4% after 10(5) s in the t-ZrO2 case. Finally, we fabricated the CTMTs with the gate stack of the t-ZrO2 case and demonstrated their characteristics as synaptic devices. With the optimization of pulse schemes, we reduced the nonlinear factors of depression (ad) and potentiation (ap) from-6.72 and 6.47 to 0.03 and 0.01 respectively, enlarged the ON/OFF ratio from 15.6 to 70.4 and increased the recognition accuracy from 27.6% to 86.5% simultaneously.
Integration of Hetero-Structure Body-Tied Ge FinFET Using Retrograde-Well Implantation
(2016)
Chou, Yu-Che
;
Hsu, Chung-Chun
;
Chun, Cheng-Ting
;
Chou, Chen-Han
;
Tsai, Ming-Li
In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I-ON/I-OFF ratio and lower junction leakage (4x10(-3)mu A/cm(2)). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6x10(-6)mu A/cm(2))as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I-ON/I-OFF ratio similar to 8x10(3) (I-S) than the conventional Ge FinFET (I-ON/I-OFF similar to 2x10 (3)).
Neuro-Inspired-in-Memory Computing Using Charge-Trapping MemTransistor on Germanium as Synaptic Device
(2020-09-01)
Chou, Yu-Che
;
Tsai, Chien-Wei
;
Yi, Chin-Ya
;
Chung, Wan-Hsuan
;
Wang, Shin-Yuan
In this work, we fabricated charge-trapping MemTransistors (CTMTs) on a germanium (Ge) substrate with a single-charge-trapping-layer gate-stack or a double-charge-trapping-layer gate-stack. We first constructed the energy band diagram of two gate stacks using transmission electron microscope (TEM) images and by X-ray photoelectron spectroscopy analysis. We deposited Al2O3 as a tunneling layer and a barrier layer using an atomic layer deposition (ALD) system while depositing HfO2 by ALD as the charge-trapping layer whose conduction band offset with respect to Al2O3 is 1.74 eV. Next, we demonstrated the memory characteristics of the CTMTs. By implementing the double-charge-trapping-layer gate-stack on the CTMT, we were able to enlarge the memory windows by 372 mV, improve the retention by 2.7%, and reduce the read disturbance. Furthermore, we demonstrated the synaptic device characteristics of the CTMTs. With the optimization of pulse schemes, we reduced the nonlinearity of potentiation (alpha(p)) and depression (alpha(d)) from 8.62 and -6.01 to 0.71 and 0.01, respectively, enlarged the ON/OFF ratio from 10.2 to 66.2, and increased the recognition accuracy from 24.5% to 82.1% simultaneously. With the implementation of the double-charge-trapping-layer gate-stack, we could further enlarge the ON/OFF ratio to 75.3 and increase the recognition accuracy to 86.5% simultaneously.