Browsing by Author "Chou, Yung-Fa"

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3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
;
Chen, Shang-Chun
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Chang, Hsiang-Hung
;
Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
Heterogeneous Chip Power Delivery Modeling and Co-Synthesis for Practical 3DIC Realization
(2017-01-01)
Liao, Wei-Hsun
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Lin, Chang-Tzu
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Fang, Sheng-Hsin
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Huang, Chien-Chia
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Chen, Hung-Ming
Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous dies power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous dies model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.
I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D ICs
(2013-01-01)
Pan, Chi-Wen
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Lee, Yu-Min
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Huang, Pei-Yu
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Yang, Chi-Ping
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Lin, Chang-Tzu
This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.
SRAM cell current in low leakage design
(2006)
Kwai, Ding-Ming
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Hsiao, Ching-Hua
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Kuo, Chung-Ping
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Chuang, Chi-Hsien
;
Hsu, Min-Chung
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 mu m 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by an order of magnitude is achievable. However, it incurs a wider cell current variation, which is pronounced only at a lower supply voltage. As the supply voltage decreases, the percent deviation from the average value increases. This can be modeled by a simple power-law relationship. The result has important implications in both design and manufacturing of the low leakage SRAM. Comparing with the generic cell current without the additional threshold voltage adjustment, the crossover point of their percent deviations at 2V signifies two separate circuit strategies: operating at 1.5V requires larger sensing margin and operating at 2.5V enjoys better manufacturability. Hence, for the applications requiring low voltage operations, it favors a boosted supply voltage applied to a selected cell during the read access.