Browsing by Author "Chu, Ann-Kuo"

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A Novel Structure to Reduce Degradation Under Mechanical Bending in Foldable Low Temperature Polysilicon TFTs Fabricated on Polyimide
(2020-05-01)
Wang, Yu-Xuan
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Chang, Ting-Chang
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Huang, Shin-Ping
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Tai, Mao-Chou
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Zheng, Yu-Zhe
In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (I-ON) increase, and an off-current (I-OFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings.
Abnormal C-V Hump Effect Induced by Hot Carriers in Gate Length-Dependent p-Type LTPS TFTs
(2019-11-01)
Huang, Shin-Ping
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Chen, Po-Hsun
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Tsao, Yu-Ching
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Chen, Hong-Chih
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Zheng, Yu-Zhe
We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) enhancement is due to the reduction of effective length, and the OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage ( ${V}_{\text {th}}$ ) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down.
An Energy-Band Model for Dual-Gate-Voltage Sweeping in Hydrogenated Amorphous Silicon Thin-Film Transistors
(2019-06-01)
Chen, Guan-Fu
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Chen, Hong-Chih
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Chang, Ting-Chang
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Huang, Shin-Ping
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Chen, Hua-Mao
This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current-gate voltage (I-D-V-G) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state -> on-state and the ON-state -> OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the I-D-V-G curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole-Frenkel region. At the Poole-Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs.
Charge trapping induced frequency-dependence degradation in n-MOSFETs with high-k/metal gate stacks
(2011-12-30)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Hung, Ya-Chi
This letter investigates the reliability issues of HfO(2)/Ti(1-x)N(x) metal-oxide-semiconductor field effect transistor in terms of static and dynamic stress. The results indicate threshold voltage (V(th)) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. Capacitance-voltage techniques verified that electron trapping under dynamic stress was located in high-k dielectric near the source/drain (S/D) overlap region, rather than the overall dielectric. Furthermore, the V(th) shift clearly increases with an increase in dynamic stress operation frequency. This phenomenon can be attributed to the fact that electrons injecting to the S/D overlap region have insufficient time to de-trap from high-k dielectric. We further investigated the impact of different Ti(1-x)N(x) composition of metal-gate electrode on charge trapping characteristics, and observed that V(th) shift decreases significantly with an increase in the ratio of nitride. This is because the nitride atoms diffusing from the metal gate fill up oxygen vacancies and reduce the concentration of traps in high-k dielectric. Crown Copyright (C) 2011 Published by Elsevier B.V. All rights reserved.
Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors
(2014-04-14)
Yang, Jyun-Bao
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Chang, Ting-Chang
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Huang, Jheng-Jie
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Chen, Yu-Chun
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Chen, Yu-Ting
In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor. (C) 2014 AIP Publishing LLC.
Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors
(2020-08-01)
Huang, Shin-Ping
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Chen, Hong-Chih
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Chen, Po-Hsun
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Zheng, Yu-Zhe
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Chu, Ann-Kuo
The extent of the poly-silicon crystalline protrusion, a result of differences in excimer laser annealing (ELA), affects the performance and reliability of thin-film transistors (TFTs). This study investigates the degradation mechanism of the low-temperature polycrystalline silicon (LTPS) TFT devices with differences in crystalline protrusion under self-heating stress (SHS). Higher ELA energy will induce higher protrusion height in the interface between the poly-silicon and gate insulator (GI). This surface morphology leads to serious charge trapping into the GI layers; in contrast, the smallest degradation after SHS can be seen in the devices with the lowest protrusion height. This indicates that the degradation is caused by the surface morphology between the poly-Si and GI interface. In addition, the COMSOL simulation results confirm that the large electric field in the GI layer appears in the rough surface morphology devices; therefore, choosing the appropriate ELA energy of the poly-Si is beneficial for the applications of the driving TFT in organic light-emitting diode (OLED) display in the manufacturing industry.
Effect of SiO2 Buffer Layer Thickness on Performance and Reliability of Flexible Polycrystalline Silicon TFTs Fabricated on Polyimide
(2016-12-01)
Chen, Bo-Wei
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Chang, Ting-Chang
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Hung, Yu-Ju
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Huang, Shin-Ping
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Chen, Hua-Mao
This letter investigates flexible polycrystalline silicon thin film transistor performance variation due to different buffer layer thicknesses. In flexible electronics, thermal expansion stress during device fabrication is inevitable. A thicker SiO2 buffer demonstrates better endurance to thermal expansion stress from the polyimide substrate during device annealing. However, if the SiO2 buffer thickness is above a critical point, its weak heat dissipation capability causes the optimal ELA crystallization condition to shift. A thermal expansion stress simulation and TEM photos were utilized to verify performance variation. Furthermore, a similar trend was observed in electrical characteristics after negative bias temperature instability.
Effects of Repetitive Mechanical Bending Strain on Various Dimensions of Foldable Low Temperature Polysilicon TFTs Fabricated on Polyimide
(2016-08)
Chen, Bo-Wei
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Chang, Ting-Chang
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Hung, Yu-Ju
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Huang, Shin-Ping
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Liao, Po-Yung
This letter investigates the effect of repeated uniaxial mechanical stress on bias-induced degradation behavior in polycrystalline thin-film transistors (TFTs). After 100 000 iterations of channel-width-direction mechanical compression, serious threshold voltage degradation and an abnormal hump are observed. Simulation indicates that the strongest mechanical stress occurs at both sides of the channel edge, between the polycrystalline silicon and gate insulator. Since these stress points produce oxide traps in the gate insulator, the degradation of threshold voltage shift and parasitic current path can be attributed to electron trapping at these intense mechanical stress points. In addition, the degradation becomes serious with diminishing TFT size.
Efficient wavelength conversion with low operation power in a Ta2O5-based micro-ring resonator
(2017-12-01)
Wu, Chung-Lun
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Huang, Jen-Yang
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Ou, Ding-Hsin
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Liao, Ting-Wei
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Chiu, Yi-Jen
The Ta2O5-based micro-ring resonator with an unloaded quality factor of 182,000 has been demonstrated to realize efficient nonlinear wavelength generation. The propagation loss of the resonator is 0.5 cm(-1), and the buildup factor of the ring resonator is estimated to be similar to 50. With a high buildup factor of the ring structure, the four-wave-mixing (FWM) conversion efficiency of -30 dB is achieved in the resonator with a pump power of 6 mW. Based on power-dependent FWM results, the nonlinear refractive index of Ta2O5 is estimated to be 1.4x10-14 cm(2)/W at a wavelength of similar to 1550 nm. The demonstration of an enhanced FWM process in the Ta(2)O(5-)based micro-ring cavity implies the possibility of realizing FWM-based optical parametric oscillation in a Ta2O5-based micro-ring resonator. (C) 2017 Optical Society of America
Enhanced gate-induced floating-body effect in PD SOI MOSFET under external mechanical strain
(2010-11-25)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Chen, Shih-Ching
The influence of tensile mechanical strain on gate-induced floating-body effect (GIFBE) in advanced partially depleted SOI n-MOSFETs was investigated. Both drain current and mobility enhance after applying strain due to the reduction of average transfer effective mass. However, it was found that the GIFBE becomes serious under the mechanical strain. To explain this phenomenon, we first clarify the mechanism of GIFBE using different operation conditions. The experiment results indicate that the GIFBE can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron band (EVB) tunneling. Based on the AHI model, the enhanced GIFBE under the mechanical strain is mainly due to the narrowing of band gap induced by the strain in the poly-gate. (C) 2010 Elsevier B.V. All rights reserved.
Enhancement of Mechanical Bending Stress Endurance Using an Organic Trench Structure in Foldable Polycrystalline Silicon TFTs
(2020-05-01)
Zheng, Yu-Zhe
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Huang, Shin-Ping
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Chen, Po-Hsun
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Chang, Ting-Chang
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Tsai, Tsung-Ming
This letter proposes a new organic trench structure which can enhance the endurance of polycrystalline silicon thin film transistors (TFTs) under mechanical bending stress. It compares conventional structure TFTs to devices with an organic trench to examine reliability after undergoing 100,000 iterations of channel width-axis (100,000'WC) compression at R = 2mm. Due to the low Young's modulus of organic materials, stress while undergoing bending strain is desorbed to the buffer layer, which can lower the overall stress in TFTs. Furthermore, an optimal location and ideal length for such an organic trench is evaluated by mechanical bending simulation.
Enhancement of the stability of resistive switching characteristics by conduction path reconstruction
(2013-07-22)
Huang, Jheng-Jie
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Chang, Ting-Chang
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Yu, Chih-Cheng
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Huang, Hui-Chun
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Chen, Yu-Ting
In this study, a Pt/BiFeO3/TiN device was fabricated and the resistance switching characteristics were investigated. After the first forming process, the conduction path was formed and exhibited unstable bipolar switching characteristics. Subsequently, the original conduction path was destroyed thoroughly by high negative bias. By reconstructing the conduction path after a second forming process (re-forming process), the device exhibits stable bipolar switching characteristics. Transmission electron microscopy analysis indicates that the stability of switching behavior was enhanced because of the joule heating effect, and is an easy way to improve the resistance switching characteristics. (C) 2013 AIP Publishing LLC.
Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2011-07-04)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Ho, Szu-Han
This paper investigates the channel hot carrier stress (CHCS) effects on gate-induced drain leakage (GIDL) current in high-k/metal-gate n-type metal-oxide-semiconductor field effect transistors. It was found that the behavior of GIDL current during CHCS is dependent upon the interfacial layer (IL) oxide thickness of high-k/metal-gate stacks. For a thinner IL, the GIDL current gradually decreases during CHCS, a result contrary to that found in a device with thicker IL. Based on the variation of GIDL current at different stress conditions, the trap-assisted band-to-band hole injection model is proposed to explain the different behavior of GIDL current for different IL thicknesses. (C) 2011 American Institute of Physics. [doi:10.1063/1.3608241]
Hot Carrier Effect on Gate-Induced Drain Leakage Current in n-MOSFETs with HfO2/Ti1-xNx Gate Stacks
(2012)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Ho, Szu-Han
"This paper investigates the effect of channel hot carrier stress (CHCS) on gate-induced drain leakage (GIDL) current in n-type metal-oxide-semiconductor field effect transistor (n-MOSFETs) with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current (Delta I-GIDL) in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the Delta I-GIDL after CHCS, and observed that the magnitude of Delta I-GIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.001206esl] All rights reserved."
Impact of Dehydrogenation Annealing Process Temperature on Reliability of Polycrystalline Silicon Thin Film Transistors
(2019-10-01)
Huang, Shin-Ping
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Chen, Po-Hsun
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Chen, Hong-Chih
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Zheng, Yu-Zhe
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Chu, Ann-Kuo
This letter investigates variations in polycrystalline silicon thin film transistor (TFT) performance under illumination and negative bias temperature instability (NBTI) tests due to different dehydrogenation annealing temperatures during the fabrication process. The depth of the density of state (DOS) in polysilicon can be indirectly determined by the TFT response to light illumination, since dangling bonds act as recombination centers. The electrical characteristics of TFTs after undergoing NBTI can also be indicative of the bonding type of silicon atoms. By analyzing the results of these reliability tests, the type of DOS can be clarified, which is beneficial for realizing the relationship between performance and reliability.
Impact of Electroforming Current on Self-Compliance Resistive Switching in an ITO/Gd:SiOx/TiN Structure
(2013-07-01)
Tseng, Hsueh-Chih
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Chang, Ting-Chang
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Wu, Yi-Chun
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Wu, Sei-Wei
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Huang, Jheng-Jie
This letter investigates self-compliance behavior for nonvolatile resistance random access memory using the indium tin oxide (ITO)/Gd:SiOx/TiN structure. Different current compliances in the electroforming process results in different trends in the set process, including a different self-compliance scale and one-or two-step set behaviors. The oxygen ions generated during the electroforming and set process drift to ITO, inducing a semiconductor-like ITO interface formation, which can be regarded as a self-built series resistor.
Impact of static and dynamic stress on threshold voltage instability in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2011-02-28)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Lo, Wen-Hung
This letter investigates the impact of static and dynamic stress on threshold voltage (V(th)) instability in ultrathin n-channel metal-oxide-semiconductor field-effect transistors with hafnium-based gate stacks. Experimental results indicate V(th) shift under dynamic stress is more serious than that under static stress due to charge trapping within the high-k dielectric. Capacitance-voltage techniques demonstrated that electron trapping under dynamic stress was located in the high-k dielectric near the source/drain overlap region rather than throughout the overall dielectric layer. This implies in real circuit operation, the phenomenon of electrons trapped in high-k near the source/drain overlap is the main issue affecting V(th) instability. (C) 2011 American Institute of Physics. [doi:10.1063/1.3560463]
Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors
(2014-10-21)
Liu, Kuan-Hsien
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Chang, Ting-Chang
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Chou, Wu-Ching
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Chen, Hua-Mao
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Tsai, Ming-Yen
This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel draininduced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast ID-VG and modulated peak/base pulse time ID-VD measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation. (C) 2014 AIP Publishing LLC.
Influence of forming process on resistance switching characteristics of In2O3/SiO2 bi-layer
(2013-01-15)
Huang, Jheng-Jie
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Chang, Ting-Chang
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Yang, Po-Chun
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Chen, Yu-Ting
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Tseng, Hsueh-Chih
In this study, we fabricated and analyzed resistance switching characteristics for resistance random access memory (RRAM) in a Pt/In2O3/SiO2/TiN structure. By applying opposing electric fields to performa soft breakdown of the In2O3/SiO2 insulating bi-layer, different switching behaviors are exhibited. When positive forming voltage was applied to the TiN electrode to soft breakdown the device, the resistance switching behavior was dominated by the bipolar mode. However, the negative voltage forming process exhibited both unipolar switching characteristics in addition to a bipolar switch mode. In order to analyze the composition of the conduction path and resistance switching mechanism, resistance value trends versus temperature was extracted and showed that the conduction paths of bipolar and unipolar modes are dominated by oxygen vacancies and metallic filament, respectively. Hence, metallic filament was considered to be formed by the migration of indium ions because the unipolar characteristic was only present during negative bias forming condition. (c) 2012 Elsevier B.V. All rights reserved.
Influence of molybdenum doping on the switching characteristic in silicon oxide-based resistive switching memory
(2013-01-28)
Chen, Yu-Ting
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Chang, Ting-Chang
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Huang, Jheng-Jie
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Tseng, Hsueh-Chih
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Yang, Po-Chun
This report compares Mo-doped and undoped SiO2 thin films of a similar thickness as well as MoOx. The Mo-doped SiO2 film exhibited switching behavior after the forming process, unlike the undoped SiO2 film. Through material analyses, a self-assembled layer is observed in the Mo-doped SiO2 film. Due to the formation of this layer, the thickness required to be broken down is effectively reduced. Subsequently, the occurrence of the switching behavior in the thinner SiO2 film further confirmed the supposition. A comparison of the two switching behaviors shows that SiO2 dominates the switching characteristic of the Mo-doped SiO2. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4790277]