Browsing by Author "Chu, Hsing-Chien"

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A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing
(2017-01-01)
Qian, Xin-Hong
;
Wu, Yi-Chung
;
Yang, Tzu-Yi
;
Cheng, Cheng-Hsiang
;
Chu, Hsing-Chien
In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted chip through the 13.56MHz wireless power and bidirectional data telemetry. The implanted chip with 4-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A and sends back the power indication and electrode impedance error signals to the external SOC. Electrical tests on the fabricated BGCI has been performed. The in-vivo animal tests on guinea pigs has shown the evoked Wave III of EABR waveforms. The proposed BGCI can be applied to patients with high-frequency hearing loss, tinnitus, and dizziness.
A Continuous-Time Delta-Sigma Modulator with Novel Data-Weighted Averaging Algorithm for Audio Application
(2015)
Lin, Jia-Ni
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Chu, Hsing-Chien
;
Chen, Zong-Yi
;
Hung, Chung-Chih
;
電機學院
A 4-bit continuous-time delta-sigma modulator (CT-DSM) with the proposed data-weighted averaging (DWA) algorithm for audio application is presented. The proposed method randomly adds one to pointer address in the DWA to reduce distortion tones and improve the performance of spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR), as compared with the conventional DWA. The post-layout simulation results show that the modulator designed in TSMC 0.18 mu m CMOS process achieves the SNDR of 81.5 dB and the dynamic range (DR) of 85dB in 24 kHz signal bandwidth. The chip area is 1.168 x 0.632 mm(2) and the power consumption is 339 mu W from a 1.8 V power supply.
A Current-Mode Dual-Slope CMOS Temperature Sensor
(2016-04-01)
Hung, Chung-Chih
;
Chu, Hsing-Chien
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電機學院
;
College of Electrical and Computer Engineering
A current-mode dual-slope CMOS temperature sensor is presented in this paper. It employs a proportional-to-absolute-temperature (PTAT) current generator, which operates in the sub-threshold region, and a novel temperature-insensitive CMOS inverter, replacing a traditional voltage comparator for power saving, to create PTAT pulsewidth. A binary counter is then utilized to quantize the pulse to a digital output value. It achieves a temperature inaccuracy of -3.39 degrees C-2 degrees C over the common industrial temperature range from -40 degrees C to 85 degrees C for five measured chip samples by utilizing the second-order curvature correction, and an average temperature resolution of 0.259 degrees C/LSB. The conversion rate of the digital output data is 3.5 kSa/s. The 2 V supply voltage is utilized and the total power dissipation is 14.286 mu W, leading to 4.082-nJ/Sa energy efficiency and 0.274-nJ degrees C-2 resolution figure of merit (FoM). It was fabricated by the TSMC 0.35-mu m CMOS process, and the core area occupies 0.0345 mm(2). The utilized dual-slope architecture has the advantages of compactness, power-saving, and high design flexibility.
A Fast-Locking All-Digital Phased-Locked Loop with a 1 ps Resolution Time-to-Digital Converter Using Calibrated Time Amplifier and Interpolation Digitally-Controlled-Oscillator
(2016)
Chu, Hsing-Chien
;
Hua, Yi-Hsiang
;
Hung, Chung-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 mu m CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.
A Novel 12-bit Current-Steering DAC with Two Reference Currents
(2015)
Chou, Fang-Ting
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Chen, Zong-Yi
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Chu, Hsing-Chien
;
Hung, Chung-Chih
;
電機學院
This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design is compact and consumes low static power. The active area of the 12-bit DAC is 0.36mm(2) approximately. This chip was fabricated by a standard 0.18 mu m CMOS technology, and consumes 38mW at 180MS/s update rate with 1.8V supply voltage.
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem
(2019-11-01)
Qian, Xin-Hong
;
Wu, Yi-Chung
;
Yang, Tzu-Yi
;
Cheng, Cheng-Hsiang
;
Chu, Hsing-Chien
Objective: To develop and verify a CMOS bone-guided cochlear implant (BGCI) microsystem with electrodes placed on the bone surface of the cochlea and the outside of round window for treating high-frequency hearing loss. Methods: The BGCI microsystem consists of an external unit and an implanted unit. The external system-on-chip is designed to process acoustic signals through an acquisition circuit and an acoustic DSP processor to generate stimulation patterns and commands that are transmitted to the implanted unit through a 13.56 MHz wireless power and bidirectional data telemetry. In the wireless power telemetry, a voltage doubler/tripler (2X/3X) active rectifier is used to enhance the power conversion efficiency and generate 2 and 3 V output voltages. In the wireless data telemetry, phase-locked loop based binary phase-shift keying and load-shift keying modulators/demodulators are adopted for the downlink and uplink data through high-Q coils, respectively. The implanted chip with four-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A. Results: Electrical tests on the fabricated BGCI microsystem have been performed to verify the chip functions. The in vivo animal tests in guinea pigs have shown the evoked third wave of electrically evoked auditory brainstem response waveforms. It is verified that auditory nerves can be successfully stimulated and acoustic hearing can be partially preserved. Conclusion and Significance: Different from traditional cochlear implants, the proposed BGCI microsystem is less invasive, preserves partially acoustic hearing, and provides an effective alternative for treating high-frequency hearing loss.
Low-Power CMOS Bandpass Filter for Application of Cochlear Prosthesis
(2016-01-01)
Chu, Hsing-Chien
;
Huang, Yu-Hua
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Hung, Chung-Chih
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電機工程學系
;
生醫電子轉譯研究中心
A CMOS Gm-C filter based on operational trans conductance amplifiers (OTA5) with low power and tuning ability for biomedical applications is proposed in this paper. The OTA works in the weak inversion region. The transconductance can be tuned by changing the bias current. A fourth-order Butterworth LC ladder Gm-C bandpass filter is implemented by 0.18 tm CMOS process. The supply voltage of the OTA-C filter can be as low as 0.65 V for minimum power dissipation. The power consumption is 61 nW for a sinusoidal input signal of 300 Hz 100 mV(PP) and 1 V supply voltage and total harmonic distortion is 50.23 dB. The active area is 0.04 mm(2).